Abstract: At least one external pin of an integrated circuit (IC) is coupled to receive a first configuration signal used in configuring an internal circuit block for a test designed to uncover faults in the circuit block, and to receive a first test signal during the test. Configuration logic in the IC is designed to generate control data by decoding configuration signals that include the first configuration signal. A test configuration register stores the control data and applies the control data during the test, but is decoupled from the configuration logic prior to commencement of the test. A sequence detector in the IC is designed to detect a reset sequence signifying an end of the test and in response to re-couple the test configuration register to the configuration logic. The number of external pins needed for testing the IC is reduced.