Patents by Inventor Ramesh kumar Harjivan Kakkad

Ramesh kumar Harjivan Kakkad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240234142
    Abstract: A method of forming a silicon film includes forming an amorphous, intrinsic, silicon layer on a substrate, forming a nickel pattern on the silicon layer, forming a first doped silicon region by doping phosphorus into a region of the silicon layer, and annealing to crystallize the silicon layer, the crystallization propagating by nickel induced lateral crystal growth starting from a portion of the silicon layer directly adjacent the nickel pattern on a first side of the first doped silicon region, propagating through the first doped silicon region to a second side of the first doped silicon region, and subsequently propagating to crystallize regions of the silicon layer to the second side of the first doped silicon region, the crystallization propagation through the first doped silicon region resulting in reduced nickel concentration, thereby forming a reduced nickel-concentration crystallized silicon layer to the second side of the first doped silicon region.
    Type: Application
    Filed: October 23, 2023
    Publication date: July 11, 2024
    Inventor: Ramesh Kumar Harjivan Kakkad
  • Publication number: 20240136182
    Abstract: A method of forming a silicon film includes forming an amorphous, intrinsic, silicon layer on a substrate, forming a nickel pattern on the silicon layer, forming a first doped silicon region by doping phosphorus into a region of the silicon layer, and annealing to crystallize the silicon layer, the crystallization propagating by nickel induced lateral crystal growth starting from a portion of the silicon layer directly adjacent the nickel pattern on a first side of the first doped silicon region, propagating through the first doped silicon region to a second side of the first doped silicon region, and subsequently propagating to crystallize regions of the silicon layer to the second side of the first doped silicon region, the crystallization propagation through the first doped silicon region resulting in reduced nickel concentration, thereby forming a reduced nickel-concentration crystallized silicon layer to the second side of the first doped silicon region.
    Type: Application
    Filed: October 22, 2023
    Publication date: April 25, 2024
    Inventor: Ramesh Kumar Harjivan Kakkad
  • Publication number: 20230420254
    Abstract: A method of producing a reduced-defect density crystalline silicon film includes forming a Six1Ge1-x1 film on a substrate, forming a Six2Ge1-x2 film on the Six1Ge1-x1 film, forming a silicon film on the Six2Ge1-x2 film, and annealing to crystallize the Six1Ge1-x1, Six2Ge1-x2, and silicon films. The values of x1 and x2 are between zero and one. The Six1Ge1-x1 and Six2Ge1-x2 films are amorphous at formation, having a first thermal budget and a second thermal budget, respectively, for crystallization, the second thermal budget lower than the first thermal budget, the Six2Ge1-x2 film spaced apart from the substrate by the Six1Ge1-x1 film. A crystalline silicon TFT device includes a substrate, a crystallized Six1Ge1-x1 layer on the substrate, a crystallized Six2Ge1-x2 layer on the crystallized Six1Ge1-x1 layer, a crystallized silicon layer on the Six2Ge1-x2 layer, a gate insulator layer on the crystallized silicon layer, and a gate electrode on the gate insulator layer.
    Type: Application
    Filed: September 13, 2023
    Publication date: December 28, 2023
    Inventor: Ramesh Kumar Harjivan Kakkad
  • Publication number: 20230420253
    Abstract: A method of producing a polycrystalline silicon TFT includes forming nickel patterns on a substrate, forming a phosphorus doped silicon layer over the substrate and nickel patterns, and forming an intrinsic silicon layer on the phosphorus doped silicon layer. Alternatively, the intrinsic silicon layer can be formed on the substrate, the phosphorus doped silicon layer on the intrinsic silicon layer, and the nickel patterns on the phosphorus doped silicon layer. The structure is annealed to crystallize the phosphorus doped silicon and intrinsic silicon layers. A method of forming a crystalline silicon layer of a TFT device includes forming a first silicon film, forming a phosphorus doped silicon film on the first silicon film, forming a nickel film on the phosphorus doped silicon film, and annealing the structure to crystallize the phosphorus doped silicon and first silicon films. The first silicon and phosphorous doped silicon films are amorphous at formation.
    Type: Application
    Filed: September 13, 2023
    Publication date: December 28, 2023
    Inventor: Ramesh Kumar Harjivan Kakkad
  • Patent number: 11791159
    Abstract: A method of producing a crystalline silicon film includes forming a first silicon film that is amorphous at formation, forming a doped film of silicon or germanium on the first silicon film, the doped film being amorphous at formation; and annealing the structure to crystallize the doped film and the first silicon film. A method of producing a crystalline silicon film includes forming a Six1Ge1-x1 film on a substrate, forming a Six2Ge1-x2 film on the Six1Ge1-x1 film, the Six1Ge1-x1 film being amorphous at formation and having a first thermal budget for crystallization, the Six2Ge1-x2 film being amorphous at formation and having a second thermal budget for crystallization, the second thermal budget being lower than the first thermal budget, forming a silicon film on the Six2Ge1-x2 film, the silicon film being amorphous at formation; and annealing to crystallize the Six1Ge1-x1 film, the Six2Ge1-x2 film, and the silicon film.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: October 17, 2023
    Inventor: Ramesh kumar Harjivan Kakkad
  • Patent number: 11562903
    Abstract: A method of producing a reduced-defect density crystalline silicon film includes forming a first intrinsic silicon film on a substrate, forming a doped film including silicon or germanium on the first intrinsic silicon film, forming a second intrinsic silicon film on the doped film, and annealing to crystallize the doped film, the second intrinsic silicon film, and the first intrinsic silicon, wherein each film is amorphous at formation, wherein crystallization initiates within the doped film. A method of forming a thin film transistor includes forming an active layer in the crystallized second intrinsic silicon layer by doping the crystallized second intrinsic silicon layer in selected areas to form source and drain regions separated by a channel portion, forming a gate insulator layer on the crystallized second intrinsic silicon layer, and forming a gate electrode pattern over the gate insulator layer.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: January 24, 2023
    Inventor: Ramesh kumar Harjivan Kakkad
  • Publication number: 20200357638
    Abstract: A method of producing a crystalline silicon film includes forming a first silicon film that is amorphous at formation, forming a doped film of silicon or germanium on the first silicon film, the doped film being amorphous at formation; and annealing the structure to crystallize the doped film and the first silicon film. A method of producing a crystalline silicon film includes forming a Six1Ge1-x1 film on a substrate, forming a Six2Ge1-x2 film on the Six1Ge1-x1 film, the Six1Ge1-x1 film being amorphous at formation and having a first thermal budget for crystallization, the Six2Ge1-x2 film being amorphous at formation and having a second thermal budget for crystallization, the second thermal budget being lower than the first thermal budget, forming a silicon film on the Six2Ge1-x2 film, the silicon film being amorphous at formation; and annealing to crystallize the Six1Ge1-x1 film, the Six2Ge1-x2 film, and the silicon film.
    Type: Application
    Filed: July 24, 2020
    Publication date: November 12, 2020
    Inventor: Ramesh kumar Harjivan Kakkad
  • Publication number: 20200234956
    Abstract: A method of producing a reduced-defect density crystalline silicon film includes forming a first intrinsic silicon film on a substrate, forming a doped film including silicon or germanium on the first intrinsic silicon film, forming a second intrinsic silicon film on the doped film, and annealing to crystallize the doped film, the second intrinsic silicon film, and the first intrinsic silicon, wherein each film is amorphous at formation, wherein crystallization initiates within the doped film. A method of forming a thin film transistor includes forming an active layer in the crystallized second intrinsic silicon layer by doping the crystallized second intrinsic silicon layer in selected areas to form source and drain regions separated by a channel portion, forming a gate insulator layer on the crystallized second intrinsic silicon layer, and forming a gate electrode pattern over the gate insulator layer.
    Type: Application
    Filed: January 17, 2020
    Publication date: July 23, 2020
    Inventor: Ramesh kumar Harjivan Kakkad