Patents by Inventor Ramesh Kumar Panwar

Ramesh Kumar Panwar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9413660
    Abstract: In one embodiment, a method includes receiving a value associated with a data packet and identifying a data set based on the value. The data set is associated with a range of values and represents routing actions. The data set is a first data set from a plurality of data sets if the value is included in the range of values associated with the first data set. The data set is a default data set if the value is not included in a range of values associated with a data set from the plurality of data sets. The method includes combining the first data set with the default data set if the first data set is identified. The method includes combining the default data set with an except data set if the default data set is identified.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: August 9, 2016
    Assignee: Juniper Networks, Inc.
    Inventors: Deepak Goel, Ramesh Kumar Panwar, Srinivasan Jagannadhan
  • Patent number: 6105128
    Abstract: A first embodiment provides an apparatus including a first execution unit capable of executing a first type and a second type of ready instruction, a second execution unit capable of executing the second type of ready instruction, and a scheduler. The scheduler dispatches the instructions in waves and dispatches the first type of ready instruction to the first execution unit with a higher priority than the second type of ready instruction. The scheduler is capable of dispatching a second type of ready instruction to the second execution unit. A second embodiment provides a method of dispatching instructions in a processor having a scheduler, a first execution unit, and a second execution unit is provided. The method includes dispatching a first type of ready instruction to the first execution unit with a higher priority than dispatching a second type of ready instruction to the first execution unit in each wave.
    Type: Grant
    Filed: April 30, 1998
    Date of Patent: August 15, 2000
    Assignee: Intel Corporation
    Inventors: Robert G. Hathaway, Ramesh Kumar Panwar
  • Patent number: 5880978
    Abstract: A method for creating an output vector Z(n-1:0) from a first vector X(n-1:0) and a second vector Y(n-1:0). The second vector Y(n-1:0) is a complement of the first vector X(n-1:0). The method subdivides X into a lower-order subvector XL(m-1:0) and a higher-order subvector XH(n-1:m). If a first 1 exists in position k in XL, then Z(k) is set to 0 and all other bits in Z(m-1:0) are set to 1. If a first 1 does not exist in XL, then all bits in Z(m-1:0) are set to 1. The method also determines if a 1 exists in XL. If a 1 exists in XL, then Z(n-1:m) is masked.
    Type: Grant
    Filed: August 20, 1996
    Date of Patent: March 9, 1999
    Assignee: Intel Corporation
    Inventors: Ramesh Kumar Panwar, Ralph Portillo, Naveen Krishnamurthy