Patents by Inventor Ramesh Kumar Singh

Ramesh Kumar Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10442117
    Abstract: A vent hole cleaning system is disclosed. The cleaning system is comprised of a housing containing a work table and a support column. The system further comprises a robotic arm mounted on the support column. Further, a subsystem is mounted at an end, opposite to the support column, of the robotic arm. The subsystem may comprise a scanner configured to generate a contour profile of a mold. Further, a vision system may be mounted on the subsystem. The vision system may be communicably connected to the scanner. Further, the system may comprise a cleaning head communicably connected to the vision system and the scanner to enable precision positioning on the mold.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: October 15, 2019
    Assignees: Indian Institute of Technology Bombay, CEAT Tyres Ltd.
    Inventors: Ramesh Kumar Singh, Sachin Alya, Rinku Kumar Mittal, Adbul Rahim, Shashikant Kharat, Pratik Sampatraj Parmar, Kumar Keshav
  • Publication number: 20180297242
    Abstract: A vent hole cleaning system is disclosed. The cleaning system is comprised of a housing containing a work table and a support column. The system further comprises a robotic arm mounted on the support column. Further, a subsystem is mounted at an end, opposite to the support column, of the robotic arm. The subsystem may comprise a scanner configured to generate a contour profile of a mold. Further, a vision system may be mounted on the subsystem. The vision system may be communicably connected to the scanner. Further, the system may comprise a cleaning head communicably connected to the vision system and the scanner to enable precision positioning on the mold.
    Type: Application
    Filed: April 17, 2017
    Publication date: October 18, 2018
    Inventors: Ramesh Kumar Singh, Sachin Alya, Rinku Kumar Mittal, Adbul Rahim, Shashikant Kharat, Pratik Sampatraj Parmar, Kumar Keshav
  • Patent number: 9059723
    Abstract: Provided is a digital-to-analog converter configured to mitigate data dependent jitter of switch driver signals. The digital-to-analog converter is configured to produce data patterns of “0001000”. The digital-to-analog converter includes a digital portion that includes a digital data input component, an analog portion, and a conversion component. The conversion component includes a decoder configured to split a first data stream comprising a set of digital data into a first data sub-stream and a second data sub-stream, and a second data stream comprising another set of digital data into a third data sub-stream and a fourth data sub-stream. The conversion component also includes a first pair of drivers, a second pair of drivers, a third pair of drivers, and a fourth pair of drivers, wherein respective drivers of the first, second, third, and fourth pairs of drivers are configured to output respective data patterns comprising at least three consecutive identical bits.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: June 16, 2015
    Assignee: Applied Micro Circuits Corporation
    Inventors: Ramesh Kumar Singh, Tarun Gupta
  • Patent number: 8742849
    Abstract: A linear source follower amplifier is provided with a first metal-oxide semiconductor (MOS) field effect transistor (FET) having a gate to accept an ac input signal and a source to supply an ac output signal. A second MOS FET has a gate to accept the ac input signal, a source connected to the drain of the first MOS FET. A third MOS FET has a drain connected to the source of the first MOS FET, a gate connected to the drain of the second MOS FET, and a source connected to a first reference voltage. A fourth MOS FET has a drain and a gate connected to the drain of the second MOS FET and a source connected to the first reference voltage. A current source has an input connected to a second reference voltage, and an output connected to the drain of the first MOS FET.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: June 3, 2014
    Assignee: Applied Micro Circuits Corporation
    Inventors: Tarun Gupta, Ramesh Kumar Singh
  • Patent number: 8525556
    Abstract: A time-interleaved sample-and-hold system includes a first sample-and-hold circuit and a second sample-and-hold circuit. The first sample-and-hold circuit and the second sample-and-hold circuit share a common sampling switch. A method of remediating a timing offset between a first sample-and-hold circuit and a second sample-and-hold circuit in a time-interleaved sample-and-hold system includes switching at least one shunt capacitor disposed between two logic gates in a timing circuit to adjust a delay between a timing signal for a common sampling switch electrically coupled to the first and second sample-and-hold circuits and a timing signal for at least one of the sample-and-hold circuits.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: September 3, 2013
    Assignee: Crest Semiconductors, Inc.
    Inventors: Ramesh Kumar Singh, Yusuf Haque, Donald E. Lewis
  • Publication number: 20120194223
    Abstract: A time-interleaved sample-and-hold system includes a first sample-and-hold circuit and a second sample-and-hold circuit. The first sample-and-hold circuit and the second sample-and-hold circuit share a common sampling switch. A method of remediating a timing offset between a first sample-and-hold circuit and a second sample-and-hold circuit in a time-interleaved sample-and-hold system includes switching at least one shunt capacitor disposed between two logic gates in a timing circuit to adjust a delay between a timing signal for a common sampling switch electrically coupled to the first and second sample-and-hold circuits and a timing signal for at least one of the sample-and-hold circuits.
    Type: Application
    Filed: January 28, 2011
    Publication date: August 2, 2012
    Applicant: SIFLARE, INC.
    Inventors: Ramesh Kumar Singh, Yusuf Haque, Donald E. Lewis
  • Patent number: 7595744
    Abstract: An offset correction circuit examines a residue signal of a stage of a pipeline analog to digital converter (ADC) to determine whether a parameter which could cause offset error, needs to be adjusted. In an embodiment, the parameter is adjusted until a maximum range of the residue signal equals an expected range. In the described examples, the adjusted parameters include timing offset error (when components of an ADC sample the input signal at different time instances) and a voltage offset error (the threshold voltage at which a sub-ADC in a stage the generated sub-code changes to a next value).
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: September 29, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Nitin Agarwal, Ramesh Kumar Singh, Visvesvaraya A Pentakota, Dantes John, Supreet Joshi
  • Publication number: 20090135037
    Abstract: An offset correction circuit examines a residue signal of a stage of a pipeline analog to digital converter (ADC) to determine whether a parameter which could cause offset error, needs to be adjusted. In an embodiment, the parameter is adjusted until a maximum range of the residue signal equals an expected range. In the described examples, the adjusted parameters include timing offset error (when components of an ADC sample the input signal at different time instances) and a voltage offset error (the threshold voltage at which a sub-ADC in a stage the generated sub-code changes to a next value).
    Type: Application
    Filed: November 27, 2007
    Publication date: May 28, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nitin Agarwal, Ramesh Kumar Singh, Visvesvaraya A. Pentakota, Dantes John, Supreet Joshi
  • Patent number: 7479816
    Abstract: A delay locked loop (DLL) circuit in which situations of lock to multiple periods of a reference signal is determined by a lock detector using dummy delay elements and a duty cycle correction circuit (DCC). The lock detector, the dummy delay elements and the delay control circuit are used in a path parallel to the delay elements which generate the desired delayed signals having different delays in relation to the reference signal. Due to the use of the parallel path, the throughput performance of the DLL circuit is not impeded. In an embodiment, separate charge pumps are used by a phase comparator and the lock detector used in the parallel path.
    Type: Grant
    Filed: October 14, 2005
    Date of Patent: January 20, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Chun Chieh Lee, Ramesh Kumar Singh, Visvesvaraya A Pentakota, Abhaya Kumar
  • Patent number: 7479915
    Abstract: A comparator presents a linear load to input signals when providing a comparison output of two input signals. The comparator contains a transistor configured in a source/emitter follower configuration, and operates in the saturation region for substantially the entire range of strengths of the input signals. As a result, the comparator presents a substantially constant load to the input signals. When incorporated in circuits such as a pipeline ADC, the comparator may substantially eliminate errors due to non-linear loads.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: January 20, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Ramesh Kumar Singh, Nitin Agarwal, Abhaya Kumar, Visvesvarya Pentakota A