Patents by Inventor Ramesh MANCHANA

Ramesh MANCHANA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Intertwined well connection and decoupling capacitor layout structure for integrated circuits
    Patent number: 11244895
    Abstract: A substrate tie cell on an IC is provided. The substrate tie cell includes a diffusion region. The diffusion region is a p-type diffusion region on or within a p-type substrate, an n-type diffusion region on or within an n-type well within a p-type substrate, an n-type diffusion region on or within an n-type substrate, or a p-type diffusion region on or within a p-type well within an n-type substrate. The substrate tie cell further includes a plurality of adjacent gate interconnects (n adjacent gate interconnects) extending over the diffusion region, where n?4. The diffusion region is configured to be at one of a first voltage or a second voltage, and the gate interconnects are configured to be at an other of the first voltage or the second voltage. In one configuration, the first voltage is a power supply voltage and the second voltage is a ground voltage.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: February 8, 2022
    Assignee: QUALCOMM INCORPORATED
    Inventors: Ramesh Manchana, Sudheer Chowdary Gali, Biswa Ranjan Panda, Dhaval Sejpal, Stanley Seungchul Song
  • INTERTWINED WELL CONNECTION AND DECOUPLING CAPACITOR LAYOUT STRUCTURE FOR INTEGRATED CIRCUITS
    Publication number: 20210375747
    Abstract: A substrate tie cell on an IC is provided. The substrate tie cell includes a diffusion region. The diffusion region is a p-type diffusion region on or within a p-type substrate, an n-type diffusion region on or within an n-type well within a p-type substrate, an n-type diffusion region on or within an n-type substrate, or a p-type diffusion region on or within a p-type well within an n-type substrate. The substrate tie cell further includes a plurality of adjacent gate interconnects (n adjacent gate interconnects) extending over the diffusion region, where n?4. The diffusion region is configured to be at one of a first voltage or a second voltage, and the gate interconnects are configured to be at an other of the first voltage or the second voltage. In one configuration, the first voltage is a power supply voltage and the second voltage is a ground voltage.
    Type: Application
    Filed: June 1, 2020
    Publication date: December 2, 2021
    Inventors: Ramesh MANCHANA, Sudheer Chowdary GALI, Biswa Ranjan PANDA, Dhaval SEJPAL, Stanley Seungchul SONG