Abstract: An emulation system comprises an outband traffic generating device comprising at least one field programmable gate array coupled to a host system. The outband traffic generating device is configured to transfer one or more bits via an outband channel to a register of an inband traffic generating device. The inband traffic generating device comprises at least one field programmable gate array coupled to a target system. The inband traffic generating device is configured to transfer the one or more bits via an inband channel to the outband traffic generating device.

Abstract: An electronic system is described herein, the apparatus including at least two devices requiring access to memory, a memory controller, and a memory, the memory being coupled to an output of the memory controller. The memory controller includes at least one input and at least one output; one memory controller input being operatively coupled to at least one of the devices through a shared bus, and one memory controller output being operatively coupled to at least one device through a shared bus. The shared bus includes a plurality of device select lines, a plurality of address lines, a plurality of write data lines, a plurality of read data lines, a plurality of read select lines, and at least two device_request lines.

Abstract: Apparatus for processing memory access requests includes first and second state machines for controlling access to first and second memory banks and an arbiter. While the first state machine is processing a current memory access request for the first memory bank, the arbiter recieves a next memory access and determines wheather the next memory access request will interfere with the processing of the current memory access request. If no interference will occur, and if the next access request is directed to the second memory bank, the second state machine begins processing he next memory access request before completion of processing of the current memory access request. The second state machine begins processing of the next memory access request during a mandatory wait period implemented by the first state machine. The first and second state machines process the current and next memory access request concurrently.