Abstract: In general, this disclosure describes techniques of ensuring cache coherency in a multi-processor computing system. More specifically, a relaxed coherency mechanism is described that provides the appearance of strong coherency and consistency to correctly written software executing on the multi-processor system. The techniques, as described herein, combine software synchronization instructions with certain hardware-implemented instructions to ensure cache coherency.

Abstract: In one embodiment, a method, comprising producing a first policy vector based on a first portion of a data packet received at a multi-stage switch. The method also includes producing a second policy vector based on a second portion of the data packet different than the first portion of the data packet. A third policy vector is produced based on a combination of at least the first policy vector and at least the second policy vector. The third policy vector including a combination of bit values configured to trigger an element at the multi-stage switch to process the data packet.

Abstract: In one embodiment, a method includes receiving a key associated with a portion of a data packet, comparing the key to a first range extreme, selecting a second range extreme, and comparing the key with the second range. The first range extreme is associated with a first range and the second range is associated with a second range. The second range is selected based on the comparing the key to the first range extreme. The method includes producing a policy vector associated with the first or second range.

Abstract: A network content service apparatus includes a set of compute elements adapted to perform a set of network services; and a switching fabric coupling compute elements in said set of compute elements. The set of network services includes firewall protection, Network Address Translation, Internet Protocol forwarding, bandwidth management, Secure Sockets Layer operations, Web caching, Web switching, and virtual private networking. Code operable on the compute elements enables the network services, and the compute elements are provided on blades which further include at least one input/output port.

Abstract: In general, this disclosure describes techniques of storing data in and retrieving data from a cache of a computing device. More specifically, techniques are described for utilizing a “perfect hash” function to implement an associative cache within a computing device. That is, the associative cache implements a fully associative map between a predetermined set of addresses and data values, employing only a single tag fetch comparison.

Abstract: In one embodiment, a method includes receiving a portion of a hash key vector. The hash key vector can be defined based on a range value and based on at least a portion of an address value from a data packet queued within a multi-stage switch. The method also includes defining, based on the hash key vector, a hash value associated with a location in a hash table when the portion of the hash key vector matches a bit vector stored in a tag table.

Abstract: In one embodiment, an apparatus can include a policy vector module configured to retrieve a compressed policy vector based on a portion of a data packet received at a multi-stage switch. The apparatus can also include a decompression module configured to receive the compressed policy vector and configured to define a decompressed policy vector based on the compressed policy vector. The decompressed policy vector can define a combination of bit values associated with a policy.

Abstract: In one embodiment, a method, comprising producing a first policy vector based on a first portion of a data packet received at a multi-stage switch. The method also includes producing a second policy vector based on a second portion of the data packet different than the first portion of the data packet. A third policy vector is produced based on a combination of at least the first policy vector and at least the second policy vector. The third policy vector including a combination of bit values configured to trigger an element at the multi-stage switch to process the data packet.

Abstract: This disclosure describes techniques of determining whether a symbol stream includes a pattern defined by a regular expression. As described herein, the regular expression may be represented using a non-deterministic finite automaton (NFA). A plurality of states in the NFA may be evaluated in parallel. These states may be associated with a plurality of symbol positions in a symbol stream. Evaluating a plurality of states and symbols in parallel may allow for faster determinations of whether the symbol stream includes the pattern defined by the regular expression.

Abstract: A network content service apparatus includes a set of compute elements adapted to perform a set of network services; and a switching fabric coupling compute elements in said set of compute elements. The set of network services includes firewall protection, Network Address Translation, Internet Protocol forwarding, bandwidth management, Secure Sockets Layer operations, Web caching, Web switching, and virtual private networking. Code operable on the compute elements enables the network services, and the compute elements are provided on blades which further include at least one input/output port.

Abstract: An architecture for controlling a multiprocessing system to provide at least one network service to subscriber data packets transmitted in the system using a plurality of compute elements, comprising a management compute element including service set-up information for at least one service and at least one processing compute element applying said at least one network service to said data packets and communicating service set-up information with the management compute element in order to perform service specific operations on data packets. In a further embodiment, a method of controlling a processing system including a plurality of processors is disclosed.

Abstract: A network content service apparatus includes a set of compute elements adapted to perform a set of network services; and a switching fabric coupling compute elements in said set of compute elements. The set of network services includes firewall protection, Network Address Translation, Internet Protocol forwarding, bandwidth management, Secure Sockets Layer operations, Web caching, Web switching, and virtual private networking. Code operable on the compute elements enables the network services, and the compute elements are provided on blades which further include at least one input/output port.

Abstract: A method and system for detecting a pattern derived from or related to a data signature in data packets is provided. An intrusion detection module accepts a data packet and compares all or portions of the data packet with a set of data patterns. One or more data patterns may be related to, or indicate the existence of, or derived from a virus or other data structure, software code, software program, portions of content of a data packet, a universal resource locater, and/or a traffic classification indicator.

Abstract: A system and method allocate memory by a network processor system in an off-chip DRAM. Upon initiation, an on-chip DRAM controller module creates a software structure that allocates blocks of memory locations in the DRAM as packet memory blocks. As a CPU, input/output module, and intrusion detection circuit read and write packets from the DRAM across a common bus, the DRAM controller module facilitates the rapid flow of packets in and out of the DRAM. FreeLists of packet buffer blocks are maintained by both the DRAM controller and the CPU for quick access in directing the flow of packets to available packet buffer blocks.

Abstract: A compute engine's central processing unit is coupled to a coprocessor that includes application engines. The central processing unit initializes the coprocessor to perform an application, and the coprocessor initializes an application engine to perform the application. The application engine responds by carrying out the application. In performing some applications, the application engine accesses cache memory—obtaining a physical memory address that corresponds to a virtual address and providing the physical address to the cache memory. In some instances, the coprocessor employs multiple application engines to carry out an application. In one implementation, the application engines facilitate different network services, including but not limited to: 1) virtual private networking; 2) secure sockets layer processing; 3) web caching; 4) hypertext mark-up language compression; 5) virus checking; 6) firewall support; and 7) web switching.

Abstract: A system includes a plurality of processing clusters and a snoop controller. A first processing cluster in the plurality of processing clusters includes a first tier cache memory coupled to a second tier cache memory. The system employs a store-create operation to obtain sole ownership of a full cache line memory location for the first processing cluster, without retrieving the memory location from other processing clusters. The system issues the store-create operation for the memory location to the first tier cache. The first tier cache forwards a memory request including the store-create operation command to the second tier cache. The second tier cache determines whether the second tier cache has sole ownership of the memory location. If the second tier cache does not have sole ownership of the memory location, ownership of the memory location is relinquished by the other processing clusters with any ownership of the memory location.

Abstract: A compute engine includes a central processing unit coupled to a coprocessor. The coprocessor includes a media access controller engine and a data transfer engine. The media access controller engine couples the compute engine to a communications network. The data transfer engine couples the media access controller engine to a set of cache memory. In further embodiments, a compute engine includes two media access controller engines. A reception media access controller engine receives data from the communications network. A transmission media access controller engine transmits data to the communications network. The compute engine also includes two data transfer engines. A streaming output engine stores network data from the reception media access controller engine in cache memory. A streaming input engine transfers data from cache memory to the transmission media access controller engine.

Abstract: A system includes a plurality of processing clusters and a snoop controller adapted to service memory requests. The snoop controller and each processing cluster are coupled to a snoop ring. A first processing cluster forwards a memory request to the snoop controller for access to a memory location. In response to the memory request, the snoop controller places a snoop request on the snoop ring—calling for a change in ownership of the requested memory location. A second processing cluster receives the snoop request on the snoop ring. The second processing cluster generates a response to the snoop request. If the second processing cluster owns the requested memory location, the second processing cluster modifies ownership status of the requested memory location.

Abstract: A multi-processor unit includes a set of processing clusters. Each processing cluster is coupled to a data ring and a snoop ring. The unit also includes a snoop controller adapted to process memory requests from each processing cluster. The data ring enables clusters to exchange requested information. The snoop ring is coupled to the snoop controller—enabling the snoop controller to forward each cluster's memory requests to the other clusters in the form of snoop requests.

Abstract: A set of cache memory includes a set of first tier cache memory and a second tier cache memory. In the set of first tier cache memory each first tier cache memory is coupled to a compute engine in a set of compute engines. The second tier cache memory is coupled to each first tier cache memory in the set of first tier cache memory. The second tier cache memory includes a data ring interface and a snoop ring interface.