Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to generate command lists to be offloaded to accelerator circuitry. An example apparatus includes kernel duration model circuitry to predict a duration of execution of a first kernel based on a first source location, a first name, a first property of a first argument, or an occupancy of the first kernel. The example apparatus includes subsequent kernel model circuitry to predict a tuple and a dependency of a second kernel based on a second source location, a second name, a second property of a second argument, or a time of submission of the previous kernel. The example apparatus includes reinforcement learning model circuitry to determine whether to bundle the first kernel into a command list based on the duration of execution of the first kernel, the tuple of the second kernel, or the dependency of the second kernel.

Abstract: Methods and apparatus to create software basic block layouts are disclosed. In one example, a method identifies branch data associated with a plurality of machine accessible instructions and identifies a plurality of basic blocks associated with the branch data. The method generates a partial layout from the plurality of basic blocks and generates a substantial layout from the partial layout based on a cost metric.

Abstract: A memory addressing technique using load buffers is described. More particularly, embodiments of the invention relate to a method and apparatus for accessing data in a computer system by exploiting addressing mode information within an instruction such that if present, data may be obtained from the load buffers, rather than accessing a cache memory or other memory device within the computer system.

Abstract: A memory addressing technique using load buffers to improve data access performance. More particularly, embodiments of the invention relate to a method and apparatus to improve cache access performance in a computer system by exploiting addressing mode information within an instruction accessing a cache memory or other memory device within the computer system.

Abstract: Methods and apparatus to perform distributed memory checking for distributed applications are disclosed. An example method comprises sending data from a first process to a second process, and sending distributed memory check data to the second process, wherein the distributed memory check data represents an initialization state of the data at the first process.

Abstract: In one aspect, a communication may be received from a debugger. The communication may specify an argument that pertains to an un-translated code. Information may also be received from a dynamic translation system. The information received from the dynamic translation system may be used to relate the argument pertaining to the un-translated code to an argument pertaining to a translated code. Then a call corresponding to the received communication may be provided to an operating system. The call may specify the argument pertaining to the translated code.

Abstract: A memory addressing technique using load buffers to improve data access performance. More particularly, embodiments of the invention relate to a method and apparatus to improve cache access performance in a computer system by exploiting addressing mode information within an instruction accessing a cache memory or other memory device within the computer system.

Abstract: A method for setting a breakpoint includes the following: receiving an input specifying a location for insertion of a breakpoint in the executable program; determining a breakpoint address for insertion of the breakpoint in the executable program based on the specified location of the breakpoint; writing a breakpoint instruction into a second machine-accessible medium at the breakpoint address; and locking a line containing the breakpoint instruction into the second machine-accessible medium to prevent the breakpoint instruction from being overwritten.

Abstract: Methods and apparatus to create software basic block layouts are disclosed. In one example, a method identifies branch data associated with a plurality of machine accessible instructions and identifies a plurality of basic blocks associated with the branch data. The method generates a partial layout from the plurality of basic blocks and generates a substantial layout from the partial layout based on a cost metric.

Abstract: A method including analyzing a program to obtain information about variables within the program, generating a call graph based on the information, determining all possible aliases for each variable, identifying parallel accesses by two variables, a variable and an alias, and/or two aliases during an instruction in the program, generating an interference graph based on the parallel accesses, and assigning the variables to logical stacks based on the interference graph.

Abstract: A memory addressing technique using load buffers-to improve data access performance. More particularly, embodiments of the invention relate to a method and apparatus to improve cache access performance in a computer system by exploiting addressing mode information within an instruction accessing a cache memory or other memory device within the computer system.

Abstract: A new branch notification processor instruction may be added to a pipelined processor with static branch prediction. The instruction may be used to instruct the processor to fetch the instruction at the branch's target.

Abstract: A method and apparatus to compact trace in a trace buffer are described.

Abstract: In a modified Harvard architecture, conventionally, read operations in the same cycle are only implemented when different memory banks are to be accessed by the different read operation. However, when different sublines in the same memory bank are being accessed, cycles may be saved by accessing both sublines in the same cycle.