Abstract: A method is provided for transmitting a digital signal between at least two transmitters and at least one receiver, using a concatenation of at least two codes. The method includes a first encoding step, in the transmitters, which outputs at least two first code words; a first transmission step of the first code words, via at least two distinct transmission channels; a receiving step, in at least one relay device, of at least two of the first code words, known as intermediate code words; a step of intertwining at least one part of the bits of the intermediate code words that outputs the intertwined bits; a second step of encoding the intertwined bits, in the relay(s), which outputs at least one second code word, taking into consideration the intermediate code words; a second step of transmitting the second code word(s) through the relay device(s), so as to enable, in the receiver(s), an iterative decoding, taking into account the first code words, and then a redundancy formed by the second code word(s).

Abstract: A method is provided for transmitting a digital signal between at least two transmitters and at least one receiver, using a concatenation of at least two codes. The method includes a first encoding step, in the transmitters, which outputs at least two first code words; a first transmission step of the first code words, via at least two distinct transmission channels; a receiving step, in at least one relay device, of at least two of the first code words, known as intermediate code words; a step of intertwining at least one part of the bits of the intermediate code words that outputs the intertwined bits; a second step of encoding the intertwined bits, in the relay(s), which outputs at least one second code word, taking into consideration the intermediate code words; a second step of transmitting the second code word(s) through the relay device(s), so as to enable, in the receiver(s), an iterative decoding, taking into account the first code words, and then a redundancy formed by the second code word(s).

Abstract: The invention concerns a module for decoding a concatenated code, corresponding at least to two elementary codes C1 and C2, using storage means (81, 83, 90, 111, 113) wherein are stored samples of data to be decoded, comprising at least two elementary decoders (821, 822, . . . 82m) of at least one of the elementary codes, the elementary decoders associated with one of the elementary codes simultaneously processing, in parallel separate code words contained in the storage means.

Abstract: The invention concerns a module for decoding a concatenated code, corresponding at least to two elementary codes C1 and C2, using storage means (81, 83, 90, 111, 113) wherein are stored samples of data to be decoded, comprising at least two elementary decoders (821, 822, . . . 82m) of at least one of the elementary codes, the elementary decoders associated with one of the elementary codes simultaneously processing, in parallel separate code words contained in the storage means.

Abstract: The bits transmitted are coded according to the product of at least two systematic block codes. Iterative decoding is applied in order to determine, at each code word search step, a data matrix ({R}) and a decision matrix ({D}) used for the following step. The new decision matrix is determined at each step by decoding the lines or columns of the input matrix, and the new data matrix is determined taking into account the correction terms which increase the reliability of the decoding on each iteration. The coding and decoding circuits (17) are rendered programmable by a shortening technique allowing selection of the number k-X of non-redundant information bits per block to be coded. Known values are assigned to the other bits, the positions of which are uniformly distributed according to each dimension of the matrices.

Abstract: The bits transmitted are coded according to the product of at least two systematic block codes. Iterative decoding is applied in order to determine, at each code word search step, a data matrix ({R}) and a decision matrix ({D}) used for the following step. The new decision matrix is determined at each step by decoding the rows or columns of the input matrix, and the new data matrix is determined taking into account the correction terms which increase the reliability of the decoding on each iteration. The coding and decoding circuits (17) are rendered programmable by a puncturing technique allowing selection of the number of bits transmitted per coded block, the punctured bits preferably having uniformly distributed positions according to each dimension of the matrices.

Abstract: The transmitted bits are coded according to the product of at least two systematic block codes. An iterative decoding is applied in order to determine, at each code word search step, a data matrix and a decision matrix which are used for the following step. The new decision matrix is determined at each step by decoding the rows or the columns of the input matrix, and the new data matrix is determined by taking account of correction terms which increase the reliability of the decoding at each iteration. The method is especially suited for use with high-efficiency block codes.

Abstract: An integrated semiconductor device, including an insulated-gate field effect transistor biased to a constant level, has a drain-source current characteristic as a function of the gate-source voltage which exhibits a negative transconductance zone beyond a maximum, the slopes of the characteristic on both sides thereof being substantially symmetrical so that two values of the gate-source voltage which are symmetrical with respect to said maximum correspond substantially to the same value of the drain source current, and in that the transistor comprises biasing means ensuring that its operating zone is situated in the region of said characteristic around said maximum.

Abstract: An integrated semiconductor active isolator circuit which includes a negative feedback amplifier having an active semiconductor amplifier element. The control terminal of the semiconductor amplifying element defines the output of the isolator circuit and a principal conduction electrode of the semiconductor amplifying element defines an input of the isolator circuit.

Abstract: An integrated semiconductor device, including an insulated-gate field effect transistor biased to a constant level in order to obtain for the transistor an N-shaped drain-source current characteristic as a function of the drain-source voltage so that it presents a negative differential conductance zone, characterized in that it comprises means for applying, between the drain and the source of the field effect transistor, a voltage whose value is in the range of values the drain-source voltage corresponding to the negative conductance zone.

Abstract: An all-pass type active circuit, realizable in the 8-12 GHz band has an inverting stage formed by a field effect transistor Q.sub.1, to whose gate the input signal V.sub.E is applied through a resistor R constituting the resistance of an RC network, and whose gate-source capacitance C.sub.GS is constitutes the capacitance C of the RC network. The parameters of a negative feedback branch inserted between the input V.sub.E and the output V.sub.S of the inverter, including a resistor R.sub.0 and a transmission line L.sub.0, are chosen so that the elements of Z=R.sub.0, l=.tau.v, R.sub.0 =2/G.sub.M0, where Z is the characteristic impedance of L.sub.0, l is the length of L.sub.0, v is the phase velocity of propagation, .tau. is the transit time of the electrons under the gate of Q.sub.1 and G.sub.M0 is the transconductance of Q.sub.1. The phase shift between V.sub.E and V.sub.S at an operating frequency .omega. is a function of the time constant .tau. of the RC network.

Abstract: A mixer of the two-transistor type (T.sub.1, T.sub.2) arranged in series by a source S.sub.2 and a drain D.sub.1. A Gate G.sub.1 receives a radio frequency signal RF and a gate G.sub.2 a local oscillator signal L0. Matching networks R.sub.1 and R.sub.2 are provided for the respective signals RF and L0. One element of the network R.sub.3 positioned at the output (drain D.sub.2 of the transistor T.sub.2) restores a short-circuit at the frequency f.sub.L0 of the local oscillator. The instability of the input G.sub.2 of the transistor T.sub.2 is compensated for by an inductor element L inserted between the junction point of the source S.sub.2 and the drain D.sub.1 and the common-mode pole.