Abstract: A system and method for enhanced read performance of a memory storage system is disclosed. The storage system includes a first memory controller. At least one first channel of a plurality of memory modules couples to the first memory controller. At least one memory module in the at least one first channel can return data sought in a read request, if present, to the first memory controller without sending the data through each memory module in the at least one first channel. The storage system also includes a second memory controller coupled to at least one second channel of a plurality of memory modules. At least one memory module in the at least one second channel can return data sought in a read request, if present, to the second memory controller without sending the data through each memory module in the at least one second channel. The at least one second channel contains an inverse mirror copy of data stored on the first channel.

Abstract: An information handling system is disclosed and can include a processor and a memory in communication with the processor. Further, a file access monitor can be embedded within the memory. The file access monitor can monitor one or more files within the information handling system and dynamically change a file representation associated with each of the one or more files based on access patterns associated with each of the one or more files.

Abstract: Information is more efficiently distributed between master and slave information handling systems interfaced through a blocking network of switches by storing the information on switches within the blocking network and distributing the information from the switches. As an example, an application distribution module located on a leaf switch distributes an application, such as an operating system, to connected slave nodes so that the slave nodes do not have to retrieve the operating system from the master node through the blocking network. For instance, a PXE boot request from a slave node to the master node is intercepted at the leaf switch to allow the slave node to boot from an image of the operating system stored in local memory of the leaf switch.

Abstract: A suspicious activity capture system can comprise a tap configured to copy network data from a communication network, and a controller coupled to the tap. The controller is configured to receive the copy of the network data from the tap, analyze the copy of the network data with a heuristic to determine if the network data is suspicious, flag the network data as suspicious based on the heuristic determination, and concurrently simulate transmission of the network data to a plurality of destination devices.

Abstract: A system and method is disclosed for optimizing the execution of a software application or other code. A computing environment may include a number of processing elements, each of which is characterized by one or more processors coupled to a single front side bus. The software application is subdivided into a number of functionally independent processes. Each process is related to a functional task of the software. Each functional process is then further subdivided on a data parallelism basis into a number of threads that are each optimized to execute on separate blocks of data. The subdivided threads are then assigned for execution to a processing element such that all of the subdivided threads associated with a functional process are assigned to a single processing element, which includes a single front side bus.

Abstract: A default setting, associated with speculative transfers of information from a main memory to a cache memory, is selected for a system based on the number of CPUs and the size of instruction and/or data caches included in the system. A matrix relating the number of processors and the size of the memory caches may be stored in a system BIOS and used to aid in determining whether the speculative transfers should be enabled or disabled by default. In general, speculative transfers will be enabled by default if system performance is more likely than not to be enhanced by using speculative transfers. Speculative transfers will be disabled if system performance is likely to be degraded by use of speculative transfers.

Abstract: A system and method is disclosed that provides for the dynamic striping of the disks of a storage array. The system and method disclosed herein provides a technique for translating access commands in a manner that is specific to the stripe that is the target of the access command. When a storage controller receives the access command, the storage controller identifies the logical block that is the subject of the access command, and the stripe that includes the logical block. On the basis of the identification of the stripe, the storage controller retrieves a stripe-specific translation function, the input of which is the logical address of the access command. After the storage controller executes the stripe-specific translation function, the storage controller completes the access command at the translated address.

Abstract: A system and method for enhanced read performance of a memory storage system is disclosed. The storage system includes a first memory controller. At least one first channel of a plurality of memory modules couples to the first memory controller. At least one memory module in the at least one first channel can return data sought in a read request, if present, to the first memory controller without sending the data through each memory module in the at least one first channel. The storage system also includes a second memory controller coupled to at least one second channel of a plurality of memory modules. At least one memory module in the at least one second channel can return data sought in a read request, if present, to the second memory controller without sending the data through each memory module in the at least one second channel. The at least one second channel contains an inverse mirror copy of data stored on the first channel.

Abstract: An information handling system includes a processor able to support a 64 bit operating system. The information handling system includes a memory resource in communication with the processor that is able to manage the memory resource as virtual memory for applications run by the processor. The information handling system includes a 32 bit application that can be run by the processor and a wrapper able to automatically determine whether the 32 bit application is Large Address Aware. If the wrapper determines that the 32 bit application is not Large Address Aware, the wrapper automatically modifies a Large Address Aware flag associated with the selected 32 bit application to allow the 32-bit application to take advantage of the additional virtual addressing capability of the 64 bit operating system.

Abstract: A user may establish initial hardware pre-fetch and second sector pre-fetch settings, including threshold values and enables status for each. Based on a comparison of various metrics associated with processor performance and the threshold values, the enable status of hardware and/or second sector pre-fetching may be changed without requiring a system reboot (or processor reinitialization).

Abstract: Frame Relay connectivity is provided via point to multipoint networks. Frame Relay access can thus be readily provided via point to multipoint networks such as data over cable networks and wireless networks. The end user obtains Frame Relay quality-of-service features via the point to multipoint network. The network service provider gains an additional method of access to the Frame Relay wide area network (WAN). Frame Relay quality of service information is translated into parameters appropriate for use with point to multipoint protocols so that point to multipoint network bandwidth may be properly measured.

Abstract: A system and method is disclosed for disabling a hyper-threading mode in the processor of a computer system when it is determined that the processor of the computer system is being adversely affected by the execution of a software application in a multi-threaded execution mode. The system and method disclosed herein involves measurement or certain performance metrics of the processor. On the basis of this performance data, the hyper-threading functionality of the processor may be disabled.

Abstract: A default setting, associated with speculative transfers of information from a main memory to a cache memory, is selected for a system based on the number of CPUs and the size of instruction and/or data caches included in the system. A matrix relating the number of processors and the size of the memory caches may be stored in a system BIOS and used to aid in determining whether the speculative transfers should be enabled or disabled by default. In general, speculative transfers will be enabled by default if system performance is more likely than not to be enhanced by using speculative transfers. Speculative transfers will be disabled if system performance is likely to be degraded by use of speculative transfers.

Abstract: Systems and methods for retransmitting unsuccessfully transmitted data across a communication link. The retransmission mechanism may be applied to point to multipoint networks including wireless networks. Each packet is encapsulated in an ARQ frame and assigned a sequence number for the purpose of coordinating acknowledgments and retransmissions. Information as to which packets require retransmission is communicated in the form of a bitmap where each bit indicates an acknowledgment status for a given packet. Any missing packets in the received sequence are assumed to require retransmission.