Abstract: A system for increasing the data throughput of an I2C bus including a serial clock conductor (3) for conducting a serial clock signal (SCK) and a serial data conductor (2) for conducting a serial data signal (SDA) includes clock-stretching control circuitry (15) coupled to the serial clock conductor (3) for stretching the serial clock signal (SCK) by holding the serial clock conductor (3) at a predetermined level to cause a master device (10) to stop sending the serial clock signal, and circuitry (FIG. 3) in the slave device (5) for releasing stretching of the serial clock signal (SCK) in response to a determination by the slave device (5) that stretching of the serial clock signal (SCK) is unnecessary.

Abstract: An improved high performance scheme is provided with a serial peripheral interface (SPI) to enable microcontroller-based products and other components and devices to achieve a higher serial transmit and receive data rate.

Abstract: An improved high performance scheme is provided with a serial peripheral interface (SPI) to enable microcontroller-based products and other components and devices to achieve a higher serial transmit and receive data rate.

Abstract: A system for increasing the data throughput of an I2C bus including a serial clock conductor (3) for conducting a serial clock signal (SCK) and a serial data conductor (2) for conducting a serial data signal (SDA) includes clock-stretching control circuitry (15) coupled to the serial clock conductor (3) for stretching the serial clock signal (SCK) by holding the serial clock conductor (3) at a predetermined level to cause a master device (10) to stop sending the serial clock signal, and circuitry (FIG. 3) in the slave device (5) for releasing stretching of the serial clock signal (SCK) in response to a determination by the slave device (5) that stretching of the serial clock signal (SCK) is unnecessary.

Abstract: Data speed in an I2C system is increased by operating a master CPU (110) to pipeline a stop/start/address byte transfer instruction by setting a stop bit, setting a start bit, and storing an address byte, operating a control circuit (87) in response to the stop bit to automatically send a stop condition on the I2C bus, operating a timing circuit (40) to count a predetermined delay from the stop condition, and operating the control circuit (87) in response to the start bit to automatically send a start condition on I2C bus after the delay has elapsed. The control circuit (87) automatically sends the address byte on the I2C bus after the start condition has been sent.

Abstract: An I2C system includes an I2C bus which includes an SCK (serial clock) conductor and an SDA (serial data) conductor, a master device coupled to the SCK conductor and the SDA conductor for sending and receiving data signals and serial clock signals. The master device includes a CPU, clock generation circuitry, and a control circuit that is coupled to the CPU, the SCK conductor, the SDA conductor, and the clock generation circuitry. A FIFO memory is coupled between the CPU and the control circuit. The CPU executes an address/data instruction, after sending a stop condition and then a start condition on the I2C bus, by causing an address byte and a plurality of data bytes to be written into the FIFO memory, causing the address byte to be read from the FIFO memory and transmitted on the I2C bus, causing a next data byte to be read from the FIFO memory and transmitted on the I2C bus, and repeating reading and transmitting of the data bytes until all of them have been transmitted on the I2C bus.

Abstract: A method and circuit for frequency synthesis using a low drift current controlled oscillator configured to provide a wide output frequency and high accuracy are provided. An exemplary frequency synthesis circuit is configured for programmable control of a center frequency of the current controlled oscillator to provide a wide range of output frequencies with high accuracy. In accordance with an exemplary embodiment of the present invention, an exemplary circuit comprises a phase-locked loop (PLL) circuit comprising a phase detector, a charge pump, a current controlled oscillator and a divider circuit. For programmable control of the current controlled oscillator, the PLL circuit further comprises a trim digital-to-analog converter (DAC) configured to provide a trimmed current signal for control of the current controlled oscillator.

Abstract: A method and circuit for frequency synthesis using a low drift current controlled oscillator configured to provide a wide output frequency and high accuracy are provided. An exemplary frequency synthesis circuit is configured for programmable control of a center frequency of the current controlled oscillator to provide a wide range of output frequencies with high accuracy. In accordance with an exemplary embodiment of the present invention, an exemplary circuit comprises a phase-locked loop (PLL) circuit comprising a phase detector, a charge pump, a current controlled oscillator and a divider circuit. For programmable control of the current controlled oscillator, the PLL circuit further comprises a trim digital-to-analog converter (DAC) configured to provide a trimmed current signal for control of the current controlled oscillator.

Abstract: A high precision, curvature compensated bandgap reference circuit with programmable gain is provided. An exemplary bangap reference circuit comprises a curvature compensation circuit configured for compensation of the temperature coefficient characteristic of the bandgap reference circuit, and a programmable gain circuit configured for adjusting the gain the output of the curvature compensation circuit to provide a high precision reference voltage. To facilitate high precision and accuracy, each of the curvature compensation circuit and the programmable gain circuit are configured for trimming during operation/after manufacture. Trimming of the temperature compensation circuit is facilitated by a first digital-to-analog (DAC) device. The programmable gain circuit comprises a gain trimming circuit comprising a second DAC.

Abstract: A system for increasing the data throughput of an I2C bus including a serial clock conductor (3) for conducting a serial clock signal (SCK) and a serial data conductor (2) for conducting a serial data signal (SDA) includes clock-stretching control circuitry (15) coupled to the serial clock conductor (3) for stretching the serial clock signal (SCK) by holding the serial clock conductor (3) at a predetermined level to cause a master device (10) to stop sending the serial clock signal, and circuitry (FIG. 3) in the slave device (5) for releasing stretching of the serial clock signal (SCK) in response to a determination by the slave device (5) that stretching of the serial clock signal (SCK) is unnecessary.

Abstract: Data speed in an I2C system is increased by operating a master CPU (110) to pipeline a stop/start/address byte transfer instruction by setting a stop bit, setting a start bit, and storing an address byte, operating a control circuit (87) in response to the stop bit to automatically send a stop condition on the I2C bus, operating a timing circuit (40) to count a predetermined delay from the stop condition, and operating the control circuit (87) in response to the start bit to automatically send a start condition on I2C bus after the the delay has elapsed. The control circuit (87) automatically sends the address byte on the I2C bus after the start condition has been sent.

Abstract: An improved high performance scheme is provided with a serial peripheral interface (SPI) to enable microcontroller-based products and other components and devices to achieve a higher serial transmit and receive data rate. An exemplary technique utilizes a CPU and an SPI having a circular FIFO structure. To prevent the memory traffic associated with any SPI accesses from conflicting with other CPU memory accesses, the technique utilizes cycle stealing direct memory access techniques for SPI data transfers with the memory. During a CPU read/write sequence, data is read/written from/to the memory through a virtual special function register (SFR). Once the virtual SFR access is detected, all accesses are redirected to the circular FIFO buffer memory, with no additional pipelining necessary. The CPU pointers can suitably increment as appropriately controlled by hardware.

Abstract: An improved high performance scheme is provided with a serial peripheral interface (SPI) to enable microcontroller-based products and other components and devices to achieve a higher serial transmit and receive data rate. An exemplary technique utilizes a CPU and an SPI having a circular FIFO structure. To prevent the memory traffic associated with any SPI accesses from conflicting with other CPU memory accesses, the technique utilizes cycle stealing direct memory access techniques for SPI data transfers with the memory. During a CPU read/write sequence, data is read/written from/to the memory through a virtual special function register (SFR). Once the virtual SFR access is detected, all accesses are redirected to the circular FIFO buffer memory, with no additional pipelining necessary. The CPU pointers can suitably increment as appropriately controlled by hardware.

Abstract: An improved high performance scheme is provided with a serial peripheral interface (SPI) to enable microcontroller-based products and other components and devices to achieve a higher serial transmit and receive data rate. An exemplary technique utilizes a CPU and an SPI having a circular FIFO structure. To prevent the memory traffic associated with any SPI accesses from conflicting with other CPU memory accesses, the technique utilizes cycle stealing direct memory access techniques for SPI data transfers with the memory. During a CPU read/write sequence, data is read/written from/to the memory through a virtual special function register (SFR). Once the virtual SFR access is detected, all accesses are redirected to the circular FIFO buffer memory, with no additional pipelining necessary. The CPU pointers can suitably increment as appropriately controlled by hardware.

Abstract: An improved high performance scheme is provided with a serial peripheral interface (SPI) to enable microcontroller-based products and other components and devices to achieve a higher serial transmit and receive data rate. An exemplary technique utilizes a CPU and an SPI having a circular FIFO structure. To prevent the memory traffic associated with any SPI accesses from conflicting with other CPU memory accesses, the technique utilizes cycle stealing direct memory access techniques for SPI data transfers with the memory. During a CPU read/write sequence, data is read/written from/to the memory through a virtual special function register (SFR). Once the virtual SFR access is detected, all accesses are redirected to the circular FIFO buffer memory, with no additional pipelining necessary. The CPU pointers can suitably increment as appropriately controlled by hardware.