Abstract: A RF receiver system for an MRI apparatus includes a receive coil, which exhibits a total effective coil impedance composed of the coil impedance of the coil itself and a patient impedance. An analog-to-digital converter is connected to an amplifier for converting the amplified output signal from the amplifier to a digital signal for further processing. A matching network is interconnected between the receive coil and the amplifier and includes a matching system with an adjustable impedance for matching the total effective coil impedance to the lowest noise impedance, and a noise calculation unit is connected to the analog-to-digital converter for receiving the digital output signal of the converter and is configured to calculate noise of the output signal of the analog-to-digital converter and for adjusting the adjustable impedance of the matching network in order to calibrate the matching network for every patient individually before the scanning process.

Abstract: A radio frequency receiver system for an MRI apparatus is provided which includes a receive coil for being attached to a patient to be examined by the MRI apparatus exhibits a total effective coil impedance which is composed of the coil impedance of the coil itself and the patient impedance due to the patient to who the coil is attached. An amplifier which exhibits the lowest noise impedance and which is connected to the receive coil for amplifying a signal received from the receive coil and outputting an amplified output signal. An analog-to-digital converter is connected to the amplifier for converting the amplified output signal from the amplifier to a digital signal for further processing.

Abstract: A sensor circuit and method. The circuit includes a first subcircuit that includes a first sense capacitor, a first integration capacitor, and a first clock input for receiving a first digital clock signal for initiating discharge of the first integration capacitor at time T. The circuit includes a second subcircuit that includes a second sense capacitor, a second integration capacitor, and a second clock input for receiving a second digital clock signal for initiating discharge of the second integration capacitor at time T+Td. A rate of discharge of the first and second integration capacitors is at least partly determined by a capacitance of the first and second sense capacitor, respectively. At time Teval, after initiation of discharge of the first and second sense capacitors, the extent to which the first and second integration capacitors have discharged is compared. A digital signal indicating the result of the comparison is outputted.

Abstract: Aspects of the present disclosure are directed to circuits, apparatuses and methods for communicating data between capacitive-isolated devices. According to an example embodiment, an apparatus includes a transmitter circuit configured to transmit a first single-ended data signal over a first signal path. The apparatus also includes a receiver circuit. The receiver circuit includes a differential amplifier having a first input coupled to receive a second single-ended signal from a second signal path of the plurality of signal paths and includes a second input coupled to receive a reference signal from a third signal path of the plurality of signal paths. The differential amplifier outputs a third single-ended signal indicative of a voltage difference between the first and second inputs. The receiver circuit also includes a common mode suppression circuit configured to remove a common mode voltage from the first and second inputs of the differential amplifier.

Abstract: A sensor circuit and method. The circuit includes a first subcircuit that includes a first sense capacitor, a first integration capacitor, and a first clock input for receiving a first digital clock signal for initiating discharge of the first integration capacitor at time T. The circuit includes a second subcircuit that includes a second sense capacitor, a second integration capacitor, and a second clock input for receiving a second digital clock signal for initiating discharge of the second integration capacitor at time T+Td. A rate of discharge of the first and second integration capacitors is at least partly determined by a capacitance of the first and second sense capacitor, respectively. At time Teval, after initiation of discharge of the first and second sense capacitors, the extent to which the first and second integration capacitors have discharged is compared. A digital signal indicating the result of the comparison is outputted.

Abstract: Aspects of the present disclosure are directed to circuits, apparatuses and methods for communicating data between capacitive-isolated devices. According to an example embodiment, an apparatus includes a transmitter circuit configured to transmit a first single-ended data signal over a first signal path. The apparatus also includes a receiver circuit. The receiver circuit includes a differential amplifier having a first input coupled to receive a second single-ended signal from a second signal path of the plurality of signal paths and includes a second input coupled to receive a reference signal from a third signal path of the plurality of signal paths. The differential amplifier outputs a third single-ended signal indicative of a voltage difference between the first and second inputs. The receiver circuit also includes a common mode suppression circuit configured to remove a common mode voltage from the first and second inputs of the differential amplifier.

Abstract: An apparatus is provided that includes first and second ICs configured to communicate using a plurality of differential signal lines. The apparatus includes a common mode suppression circuit having a plurality of common mode voltage adjustment circuits, each configured to provide a low impedance path for common mode signals and a high impedance path for differential AC signaling, thereby suppressing the effect of common mode transients between the voltage domains. The plurality of common mode voltage adjustment circuits each have components that are impedance matched up to an impedance-tolerance specification. The common mode suppression circuit also includes an AC coupling circuit configured to be less dependent on impedance mismatch, beyond the impedance-tolerance specification, by cross coupling the impedance differentials from each of the differential signal lines through the AC coupling circuit and to one of the common mode voltage adjustment circuits.

Abstract: An apparatus is provided that includes first and second ICs configured to communicate using a plurality of differential signal lines. The apparatus includes a common mode suppression circuit having a plurality of common mode voltage adjustment circuits, each configured to provide a low impedance path for common mode signals and a high impedance path for differential AC signaling, thereby suppressing the effect of common mode transients between the voltage domains. The plurality of common mode voltage adjustment circuits each have components that are impedance matched up to an impedance-tolerance specification. The common mode suppression circuit also includes an AC coupling circuit configured to be less dependent on impedance mismatch, beyond the impedance-tolerance specification, by cross coupling the impedance differentials from each of the differential signal lines through the AC coupling circuit and to one of the common mode voltage adjustment circuits.

Abstract: In some embodiments, a receiver circuit is configured to receive a modulated signal from a transmitter that is galvanically isolated from the receiver circuit. The receiver circuit is configured to demodulate the modulated signal by using two comparator circuits that respectively detect the presence or absence of first and second signal states of a carrier signal. Based on the detection of the first and second states, the receiver circuit determines whether the carrier signal is present or absent in the modulated signal to determine a demodulated value of the modulated signal.

Abstract: In one or more embodiments, a circuit is configured to receive a differential signal from a transmitter that is isolated from the receiver circuit and that includes a common-mode suppression circuit and signal combining circuit coupled to the corresponding lines carrying the differential signals. The common-mode suppression and signal combining circuits are configured to suppress common-mode signals of differential signals communicated on the set of differential signal lines and combine to form of differential-mode components of the differential signals.

Abstract: Data is communicated. In accordance with one or more example embodiments, a communications circuit communicates a digital data signal using a carrier signal having a frequency that is different than the frequency of the data signal. The communications circuit includes first and second sets of capacitors, a first circuit and a second circuit. The first circuit generates mixed data signals respectively mixed with the carrier signal and an inverse of the carrier signal, generates mixed inverted data signals respectively mixed with the carrier signal and an inverse of the carrier signal, provides the mixed data signals to the first set of capacitors, and provides the mixed inverted data signals to the second set of capacitors. The second circuit recovers the data signal from the mixed signals.

Abstract: In one embodiment, a device includes a first IC having a differential signal driver and a first isolation circuit configured to provide differential signals transmitted by the differential signal driver to a first pair of bond pads of the first IC. First and second bond wires are configured to provide differential signals from the first pair of bond pads to a second pair of bond pad included in a second IC. The second IC includes a second isolation circuit configured to provide differential signals from the second pair of bond pads to a differential receiver circuit of the second IC. The bond wires are specifically arranged such that a distance between the first and second bond wires varies by at least 10% as measured at two points along a length of the first bond wire.

Abstract: In some embodiments, a receiver circuit is configured to receive a modulated signal from a transmitter that is galvanically isolated from the receiver circuit. The receiver circuit is configured to demodulate the modulated signal by using two comparator circuits that respectively detect the presence or absence of first and second signal states of a carrier signal. Based on the detection of the first and second states, the receiver circuit determines whether the carrier signal is present or absent in the modulated signal to determine a demodulated value of the modulated signal.

Abstract: Data is communicated. In accordance with one or more example embodiments, a communications circuit communicates a digital data signal using a carrier signal having a frequency that is different than the frequency of the data signal. The communications circuit includes first and second sets of capacitors, a first circuit and a second circuit. The first circuit generates mixed data signals respectively mixed with the carrier signal and an inverse of the carrier signal, generates mixed inverted data signals respectively mixed with the carrier signal and an inverse of the carrier signal, provides the mixed data signals to the first set of capacitors, and provides the mixed inverted data signals to the second set of capacitors. The second circuit recovers the data signal from the mixed signals.

Abstract: The invention refers to a power converter and to a method for power conversion. The power converter includes a primary winding adapted to receive a primary alternating voltage. The converter further includes a first secondary circuit magnetically coupled to the primary winding, the first secondary circuit generating a first secondary output signal, the power converter further includes a second secondary circuit magnetically coupled to the primary winding. The power converter includes a post regulator adapted to be coupled to the second secondary circuit, the post regulator having a switch which is opened at every zero-crossing of the first output signal.