Abstract: A metal oxide semiconductor (MOS) integrated circuit (IC) has a plurality of fiducial standard cells of different cell sizes. The different cell sizes are non-equally utilized. The plurality of fiducial standard cells are placed to have a random offset from a uniform global placement pattern. Each of the fiducial standard cells has at least four power rails and various sets of active regions. The power rails extend in a first direction. The active regions are provided adjacent to the power rails but are disconnected from contacts and interconnects and thus do not draw power from the power rails. Instead, the active regions are disjoint and collinear thereby creating islands of active regions among spacings of inactive regions. These inactive regions more easily allow electromagnetic radiation to pass through thereby allowing the MOS fiducial standard cell to be visible for a CAD-to-silicon backside image alignment even with 7 nm feature sizes.

Abstract: A metal oxide semiconductor (MOS) integrated circuit (IC) has a plurality of fiducial standard cells of different cell sizes. The different cell sizes are non-equally utilized. The plurality of fiducial standard cells are placed to have a random offset from a uniform global placement pattern. Each of the fiducial standard cells has at least four power rails and various sets of active regions. The power rails extend in a first direction. The active regions are provided adjacent to the power rails but are disconnected from contacts and interconnects and thus do not draw power from the power rails. Instead, the active regions are disjoint and collinear thereby creating islands of active regions among spacings of inactive regions. These inactive regions more easily allow electromagnetic radiation to pass through thereby allowing the MOS fiducial standard cell to be visible for a CAD-to-silicon backside image alignment even with 7 nm feature sizes.

Abstract: Disclosed are techniques for detecting hotspots using parameter matching. According to various implementations of the invention, devices in an electronic circuit design are classified into device groups based on their values for one or more device parameters, which can be derived from layout data describing the devices. Representative electrical information for each of the device groups is determined and used as a basis for hotspot detection.

Abstract: Aspects of the invention relate to techniques for detecting and correcting electrical hotspots in a layout design for a circuit design comprising an analog circuit. Layout parameters for device instances associated with electrical constraints are first extracted. Based on the extracted layout parameters, electrical parameter variations for the device instances may be computed to identify one or more electrical hotspots in the layout design. A sensitivity analysis of the one or more electrical hotspots is performed to generate repair hints. Based on the repair hints, the layout design is adjusted.

Abstract: Aspects of the invention relate to techniques for detecting and correcting electrical hotspots in a layout design for a circuit design comprising an analog circuit. Layout parameters for device instances associated with electrical constraints are first extracted. Based on the extracted layout parameters, electrical parameter variations for the device instances may be computed to identify one or more electrical hotspots in the layout design. A sensitivity analysis of the one or more electrical hotspots is performed to generate repair hints. Based on the repair hints, the layout design is adjusted.

Abstract: Disclosed are techniques for detecting hotspots using parameter matching. According to various implementations of the invention, devices in an electronic circuit design are classified into device groups based on their values for one or more device parameters, which can be derived from layout data describing the devices. Representative electrical information for each of the device groups is determined and used as a basis for hotspot detection.

Abstract: A system and method for determining whether a desired integrated circuit layout can be accurately modeled from a resist model that is calibrated from a mask test pattern. In one embodiment, a chessboard graph is created having horizontal and vertical axes that are assigned two imaging parameters calculated from the test mask data and the desired integrated circuit layout data. Data on the horizontal and vertical axes of the chessboard graph are divided into a number of ranges or bins. The intersection of each bin on the horizontal and vertical axis is associated with a subgraph that plots the relation between two additional imaging parameters having values of the first two imaging parameters in the ranges of the intersecting bin.

Abstract: A system and method for determining whether a desired integrated circuit layout can be accurately modeled from a resist model that is calibrated from a mask test pattern. In one embodiment, a chessboard graph is created having horizontal and vertical axes that are assigned two imaging parameters calculated from the test mask data and the desired integrated circuit layout data. Data on the horizontal and vertical axes of the chessboard graph are divided into a number of ranges or bins. The intersection of each bin on the horizontal and vertical axis is associated with a subgraph that plots the relation between two additional imaging parameters having values of the first two imaging parameters in the ranges of the intersecting bin.