Patents by Inventor Ramin Farjad

Ramin Farjad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10673561
    Abstract: A BASE-T Ethernet transceiver is disclosed. The transceiver includes a BASE-T Ethernet transmit circuit that employs a data framing module. The data framing module includes an input interface to receive Ethernet block data bits, and, forward error correction encoder is coupled to the logic to encode at least a first portion of the data bits to generate first error check bits. A Reed-Solomon (RS) encoder is coupled to the logic to encode at least a second portion of the data bits in accordance with a Reed-Solomon error code to generate second error check bits. A symbol mapper modulates the Ethernet block data bits in accordance with an SQ64 constellation comprising back-to-back PAM8 symbols.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: June 2, 2020
    Assignee: Marvell Asia Pte, LTD
    Inventors: Ramin Farjad, Paul Langner
  • Publication number: 20180322495
    Abstract: Disclosed is a computer-implemented banking system for the visually-challenged. The system comprises a user terminal comprising an output means for perceivably-delivering to a user, a user-selected form from a plurality of banking forms, the form delivered one query at a time and an input means for receiving user input as a response to each query. The system further comprises a preview module for perceivably-delivering the user-inputted form, via the output means, to the user for preview and an authentication module for receiving the user's authentication upon the user finalizing the previewed form, wherein the authentication is associated with the form.
    Type: Application
    Filed: January 15, 2018
    Publication date: November 8, 2018
    Inventors: Ramin Farjad, Saeed Sadeghpour Vajdi, Arman Bahri
  • Patent number: 9893756
    Abstract: An Ethernet transceiver integrated circuit (IC) chip is disclosed. The IC chip includes multiple physical sub-channels, where each sub-channel transfers data symbols along a wired link. Each data symbol representing a group of multiple data bits. Logic determines a signal quality parameter value for each of the sub-channels. For each sub-channel, in a first mode where a given sub-channel exhibits a signaling quality above a first predetermined threshold, the logic assigns a modulation of a first type associated with a first constellation. In a second mode where a given sub-channel exhibits a signaling quality below the first predetermined threshold, the logic assigns a modulation of a second type associated with a second constellation that is sparser than the first constellation.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: February 13, 2018
    Assignee: Aquantia Corp.
    Inventors: Hossein Sedarat, Ramin Farjad
  • Patent number: 9853769
    Abstract: A BASE-T Ethernet transceiver is disclosed. The transceiver includes a BASE-T Ethernet transmit circuit that employs a data framing module. The data framing module includes an input interface to receive Ethernet block data bits, and, forward error correction encoder is coupled to the logic to encode at least a first portion of the data bits to generate first error check bits. A Reed-Solomon (RS) encoder is coupled to the logic to encode at least a second portion of the data bits in accordance with a Reed-Solomon error code to generate second error check bits. A symbol mapper modulates the Ethernet block data bits in accordance with an SQ64 constellation comprising back-to-back PAM8 symbols.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: December 26, 2017
    Inventors: Ramin Farjad, Paul Langner