Abstract: A technique for pinpointing and analyzing failures in complex integrated circuits is disclosed. A tester stimulates the a device (DUT) with input patterns. DUT output patterns are communicated back to the tester, and are compared to simulation results. Failing outputs are identified. Working back from the failing output, suspect failing nodes are identified in a schematic editor. Through a layout database linked to the schematic editor, the position of each suspect failing node is identified. A probe and SEM are positioned at nodes suspected of causing the failure. Live waveforms generated by the probe are compared with simulated waveforms for the node, while the DUT is being re-exercised by the tester. In a windowed display environment, the user is provided with schematic, layout, SEM image, and live and simulated waveforms for the suspect node. Node after node are explored in this manner until the failing circuit element is identified. Documentation is provided by printing any and all of the windows.

Abstract: A technique for pinpointing and analyzing failures in complex integrated circuits is disclosed. A device-under-test (DUT) is powered up. Using Liquid Crystal (LC) or Photo-Emission (PE) techniques, leakage sites are identified. The leakage sites are associated with suspect circuit elements on the DUT, and candidate I/Os associated with the suspect failing elements are selected for subsequent testing. Using the candidate I/Os, a truncated set of test vectors is created, and applied to the DUT. While the DUT is running the truncated set of test vectors, the suspect elements are rigorously probed to identify failing elements. SEM images are preferably viewed simultaneously. In this manner, a log of failing elements is derived, for circuit or process re-design.