Patents by Inventor Ramin K. Poorfard

Ramin K. Poorfard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9800281
    Abstract: A signal processor for a radio frequency (RF) receiver includes a signal processing path having first and second programmable gain amplifiers and first and second offset correction circuits. The first offset correction circuit receives a first digital offset correction word and corrects a first offset of the first programmable gain amplifier by adding a first value corresponding to the first digital offset correction word to an input of the first programmable gain amplifier. The second offset correction circuit receives a second digital offset correction word and corrects a second offset of the second programmable gain amplifier by adding a first value corresponding to the second digital offset correction word to an input of the second programmable gain amplifier. A controller measures offsets of the first and second programmable gain amplifiers during a calibration, and provides the first and second offset correction words in response to the offsets.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: October 24, 2017
    Assignee: Silicon Laboratories Inc.
    Inventors: Abdulkerim L. Coban, Alessandro Piovaccari, Ramin K. Poorfard, James T. Kao
  • Publication number: 20170201282
    Abstract: A signal processor for a radio frequency (RF) receiver includes a signal processing path having first and second programmable gain amplifiers and first and second offset correction circuits. The first offset correction circuit receives a first digital offset correction word and corrects a first offset of the first programmable gain amplifier by adding a first value corresponding to the first digital offset correction word to an input of the first programmable gain amplifier. The second offset correction circuit receives a second digital offset correction word and corrects a second offset of the second programmable gain amplifier by adding a first value corresponding to the second digital offset correction word to an input of the second programmable gain amplifier. A controller measures offsets of the first and second programmable gain amplifiers during a calibration, and provides the first and second offset correction words in response to the offsets.
    Type: Application
    Filed: March 28, 2017
    Publication date: July 13, 2017
    Applicant: Silicon Laboratories Inc.
    Inventors: Abdulkerim L. Coban, Alessandro Piovaccari, Ramin K. Poorfard, James T. Kao
  • Patent number: 8874060
    Abstract: A radio frequency (RF) receiver with frequency planning includes an analog receiver, a digital processor, and a clock synthesizer. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, a signal output for providing an IF output signal, and a control output for providing a clock control signal. The clock synthesizer has an input for receiving the clock control signal, and an output for providing the clock signal, and is controllable to adjust a frequency of the clock signal to a selected one of a predetermined number of frequencies within a predetermined frequency range in response to the clock control signal.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: October 28, 2014
    Assignee: Silicon Laboratories Inc.
    Inventors: Sherry X. Wu, Mustafa H. Koroglu, Alessandro Piovaccari, Ramin K. Poorfard
  • Publication number: 20110151816
    Abstract: A radio frequency (RF) receiver with frequency planning includes an analog receiver, a digital processor, and a clock synthesizer. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, a signal output for providing an IF output signal, and a control output for providing a clock control signal. The clock synthesizer has an input for receiving the clock control signal, and an output for providing the clock signal, and is controllable to adjust a frequency of the clock signal to a selected one of a predetermined number of frequencies within a predetermined frequency range in response to the clock control signal.
    Type: Application
    Filed: December 18, 2009
    Publication date: June 23, 2011
    Applicant: Silicon Laboratories, Inc.
    Inventors: Sherry X. Wu, Mustafa H. Koroglu, Alessandro Piovaccari, Ramin K. Poorfard