Abstract: A system that detects malicious traffic flows in a network includes a computer system including a processor in communication with at least one memory device. The processor is programmed to store a plurality of context information about the network including a plurality of devices. The processor is also programmed to determine a network configuration of the network at a specific point in time. The processor is further programmed to generate one or more security policies for one or more devices of the plurality of devices in the network based on the network configuration and the plurality of context information. In addition, the processor is programmed to deploy the one or more security policies to the one or more devices in the network, wherein the one or more devices are configured to execute an algorithm to monitor communications on the network in view of a corresponding security policy of the one or more security policies.

Abstract: A system for detecting malicious traffic flows in a network is provided. The system includes a processor. Based on packet information received for a plurality of data packets transmitted over the network the processor is programmed to calculate inter-arrival times and packet durations for the plurality of data packets. The processor is also programmed to filter the packet information to remove noise. The processor is further programmed to generate at least one histogram based on the packet information, the inter-arrival times, and the packet durations. In addition, the processor is programmed to generate a power spectral density estimate based on the packet information, the inter-arrival times, and the packet durations. Moreover, the processor is programmed to analyze the at least one histogram and the power spectral density estimate to detect one or more unexpected data flows. Furthermore, the processor is programmed to report the one or more unexpected data flows.

Abstract: A system for detecting malicious traffic flows in a network is provided. The system includes a processor. Based on packet information received for a plurality of data packets transmitted over the network the processor is programmed to calculate inter-arrival times and packet durations for the plurality of data packets. The processor is also programmed to filter the packet information to remove noise. The processor is further programmed to generate at least one histogram based on the packet information, the inter-arrival times, and the packet durations. In addition, the processor is programmed to generate a power spectral density estimate based on the packet information, the inter-arrival times, and the packet durations. Moreover, the processor is programmed to analyze the at least one histogram and the power spectral density estimate to detect one or more unexpected data flows. Furthermore, the processor is programmed to report the one or more unexpected data flows.

Abstract: A system that detects malicious traffic flows in a network includes a computer system including a processor in communication with at least one memory device. The processor is programmed to store a plurality of context information about the network including a plurality of devices. The processor is also programmed to determine a network configuration of the network at a specific point in time. The processor is further programmed to generate one or more security policies for one or more devices of the plurality of devices in the network based on the network configuration and the plurality of context information. In addition, the processor is programmed to deploy the one or more security policies to the one or more devices in the network, wherein the one or more devices are configured to execute an algorithm to monitor communications on the network in view of a corresponding security policy of the one or more security policies.

Abstract: A network for a large number of processing elements utilizes a trellis ring architecture to provide an efficient and fault tolerant data routing system. The processing elements (which may be chip-based processors, circuit cards, unit level assemblies, or computing devices) are interconnected together in an endless ring structure. In addition to the ring arrangement, the processing elements are interconnected via primary and additional trellis connections that reduce the average and/or the maximum number of network node hops between two processing elements in the network architecture.

Abstract: Systems and methods for carrier phase recovery are provided. One method includes providing a reference signal, detecting an input signal and determining a Signal to Noise Ratio (SNR) of the input signal. The method also includes employing a Minimum Mean Square Error (MMSE) algorithm based on the SNR to determine a Carrier Phase Recovery Loop (CPRL) bandwidth.

Abstract: Systems and methods for carrier phase recovery are provided. One method includes providing a reference signal, detecting an input signal and determining a Signal to Noise Ratio (SNR) of the input signal. The method also includes employing a Minimum Mean Square Error (MMSE) algorithm based on the SNR to determine a Carrier Phase Recovery Loop (CPRL) bandwidth.

Abstract: A network for a large number of processing elements utilizes a trellis ring architecture to provide an efficient and fault tolerant data routing system. The processing elements (which may be chip-based processors, circuit cards, unit level assemblies, or computing devices) are interconnected together in an endless ring structure. In addition to the ring arrangement, the processing elements are interconnected via primary and additional trellis connections that reduce the average and/or the maximum number of network node hops between two processing elements in the network architecture.

Abstract: A method is disclosed for encoding and modulating bits of an information stream and transmitting them over a designated channel in a high speed communication system. The method includes the steps of dividing a set of the entire constellation of available points into a finite plurality of zero parity vectors defined by two criteria, namely that (1) the column vectors have odd parity and (2) a group of a predefined integer number of column vectors have a 0 modulus (i.e. be divisible by a given number). Column vectors forming only a partially dimensioned portion of the code (e.g. 4D) corresponding to one discrete baud interval are preferably transmitted in a systematic form and with sufficient coding gain for adaptive DFE equalization and whereby a group of column vectors corresponding to an integer number of successive baud intervals that form the fully dimensioned code (e.g.

Abstract: A multi-dimensional equalizer/decoder is disclosed for equalizing a channel transmitting electrical pulses corresponding to a plurality of interdependent symbols formed according to the rules of a multi-dimensional code (e.g. block lattice coded modulation). The symbols are received by the equalizer/decoder over multiple symbol (baud) periods because it takes more than one symbol period to receive a minimum decodable number of symbols on the given number of physical channels. The equalizer/decoder employs a preliminary and a final decision device which cooperate with the components of an "equalization layer." A plurality of equalization layers may be used if the symbols are received over a plurality of physical channels. Each equalization layer has first, second, and third, adaptive, feed forward filters, along with appropriately located buffers for collecting decodable groups of the transmitted symbols for group-by-group provision to the decision devices.

Abstract: An adaptive equalization method and device which provides for the equalization of symbol sequences sent through fading multipath channels with time and frequency dispersion. By using a trainer system to supply an estimate of the received symbol sequence to a trainee system, equalization of the received symbol sequences is accomplished without the need for training sequences and with the ability of compensating for spectral nulls without a substantial increase in the noise in the system. The trainer system is configured as a decision directed equalizer with a feed forward filter having the received symbol sequence as input and connected to a decision element that outputs decided symbols. The trainee system is similar to decision feed back equalization in that it has a feed forward filter, a feedback filter and a decision element but, differs in that the input to the feed back filter is provided by the trainer system. The feed forward filter of the trainee system takes received symbol sequence as input.

Abstract: An adaptive equalization method and device which provides for the equalization of symbol sequences sent through fading multipath channels with time and frequency dispersion. By using a trainer system to supply an estimate of the received symbol sequence to a trainee system, equalization of the received symbol sequences is accomplished without the need for training sequences and with the ability of compensating for spectral nulls without a substantial increase in the noise in the system. The trainer system is configured as a decision directed equalizer with a feed forward filter having the received symbol sequence as input and connected to a decision element that outputs decided symbols. The trainee system is similar to decision feed back equalization in that it has a feed forward filter, a feedback filter and a decision element but, differs in that the input to the feed back filter is provided by the trainer system. The feed forward filter of the trainee system takes received symbol sequence as input.