Patents by Inventor Ramin SHARIAT-YAZDI

Ramin SHARIAT-YAZDI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MEMORY ADDRESS PROTECTION CIRCUIT AND METHOD OF OPERATING SAME
    Publication number: 20230385145
    Abstract: A memory circuit includes: a memory configured to store a data unit and parity bits, the parity bits including data parity bits based on the data unit and write address parity bits based on a write address associated with the stored data unit; a write address port configured to receive the write address for the stored data unit; a first decoding circuit configured to determine when a data error exists based on the stored data unit and the data parity bits; a second decoding circuit configured to generate a decoded write address from a read address and the write address parity bits; and an error detecting circuit configured to determine when an address error exists based on a comparison of the decoded write address to the read address.
    Type: Application
    Filed: July 19, 2023
    Publication date: November 30, 2023
    Inventors: Saman M. I. ADHAM, Ramin SHARIAT-YAZDI, Shih-Lien Linus LU
  • Memory address protection circuit and method of operating same
    Patent number: 11714705
    Abstract: A memory circuit includes: a memory configured to store a data unit and parity bits, the parity bits including data parity bits based on the data unit and write address parity bits based on a write address associated with the stored data unit; a write address port configured to receive the write address for the stored data unit; a first decoding circuit configured to determine when a data error exists based on the stored data unit and the data parity bits; a second decoding circuit configured to generate a decoded write address from a read address and the write address parity bits; and an error detecting circuit configured to determine when an address error exists based on a comparison of the decoded write address to the read address.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: August 1, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Saman M. I. Adham, Ramin Shariat-Yazdi, Shih-Lien Linus Lu
  • MEMORY ADDRESS PROTECTION CIRCUIT AND METHOD OF OPERATING SAME
    Publication number: 20220334916
    Abstract: A memory circuit includes: a memory configured to store a data unit and parity bits, the parity bits including data parity bits based on the data unit and write address parity bits based on a write address associated with the stored data unit; a write address port configured to receive the write address for the stored data unit; a first decoding circuit configured to determine when a data error exists based on the stored data unit and the data parity bits; a second decoding circuit configured to generate a decoded write address from a read address and the write address parity bits; and an error detecting circuit configured to determine when an address error exists based on a comparison of the decoded write address to the read address.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Inventors: Saman M. I. ADHAM, Ramin SHARIAT-YAZDI, Shih-Lien Linus LU
  • Memory address protection circuit and method
    Patent number: 11379298
    Abstract: A circuit includes: a single-port memory interface which includes a sole address port configured to receive a read/write (RW) address, and a multi-port memory which has multiple address ports coupled to the sole address port of the single-port memory interface, and which is configured to store a data unit and parity bits, some of the parity bits being based on the corresponding RW address; a first decoding circuit configured to generate a decoded write address from the RW address and the parity bits; and an error detecting circuit configured to determine if an address error exists based on a comparison of the decoded write address to the read address.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: July 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Saman M. I. Adham, Ramin Shariat-Yazdi, Shih-Lien Linus Lu
  • MEMORY ADDRESS PROTECTION CIRCUIT AND METHOD
    Publication number: 20200371865
    Abstract: A circuit includes: a single-port memory interface which includes a sole address port configured to receive a read/write (RW) address, and a multi-port memory which has multiple address ports coupled to the sole address port of the single-port memory interface, and which is configured to store a data unit and parity bits, some of the parity bits being based on the corresponding RW address; a first decoding circuit configured to generate a decoded write address from the RW address and the parity bits; and an error detecting circuit configured to determine if an address error exists based on a comparison of the decoded write address to the read address.
    Type: Application
    Filed: August 10, 2020
    Publication date: November 26, 2020
    Inventors: Saman M. I. ADHAM, Ramin SHARIAT-YAZDI, Shih-Lien Linus LU
  • Memory address protection circuit and method
    Patent number: 10740174
    Abstract: A circuit includes a memory configured to store a data unit and parity bits, the parity bits being based on a write address associated with the stored data unit. An address port is configured to receive a read address for the stored data unit. A decoding circuit is configured to generate a decoded write address from the read address and the parity bits, and an error detecting circuit is configured to determine if an address error exists based on a comparison of the decoded write address to the read address.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: August 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Saman M. I. Adham, Ramin Shariat-Yazdi, Shih-Lien Linus Lu
  • MEMORY ADDRESS PROTECTION CIRCUIT AND METHOD
    Publication number: 20180150352
    Abstract: A circuit includes a memory configured to store a data unit and parity bits, the parity bits being based on a write address associated with the stored data unit. An address port is configured to receive a read address for the stored data unit. A decoding circuit is configured to generate a decoded write address from the read address and the parity bits, and an error detecting circuit is configured to determine if an address error exists based on a comparison of the decoded write address to the read address.
    Type: Application
    Filed: June 14, 2017
    Publication date: May 31, 2018
    Inventors: Saman M. I. ADHAM, Ramin SHARIAT-YAZDI, Shih-Lien Linus LU