Abstract: A stacked-die image sensor may be provided with an array of image pixels. The stacked-die image sensor may include at least first and second integrated circuit dies stacked on top of one another. Some of the pixel circuitry in each pixel may be formed in the first integrated circuit die and some of the pixel circuitry in each pixel may be formed in the second integrated circuit die. Coupling structures such as conductive pads may electrically couple the pixel circuitry in the first integrated circuit die to the pixel circuitry in the second integrated circuit die. A shielding structure may partially or completely surround each conductive pad to reduce parasitic capacitive coupling between adjacent conductive pads. The shielding structure may be a metal wire coupled to a ground voltage. The shielding structure may extend between columns of image pixels and/or between rows of image pixels.

Abstract: In one embodiment, a method of forming a semiconductor device may include extending a gate conductor of a transistor to overlie a boundary of a well region in which the transistor is formed. The gate conductor may extend to make electrical contact with a gate conductor of a 2nd transistor that is formed external to the well region. A contact conductor may be applied to electrically and physically contact the first and 2nd gate conductors and to also overlie the boundary of the well region.

Abstract: An image sensor may include an array of pixels, and analog and digital circuitry. The pixels in the array may generate image signals in response to incident light. The image sensor may also include power supply circuitry and corresponding voltage rail structures that provide voltage levels to operate the pixel array, the analog circuitry, and the digital circuitry. The power supply circuitry may provide a low voltage, a high voltage, and an intermediate voltage power rail. The analog circuitry may operate in a voltage level domain defined by voltages between an intermediate voltage level and a high voltage level. The digital circuitry may operate in a voltage level domain defined by voltages between a low voltage level and the intermediate voltage level. In such a configured, analog and digital circuitry may both be provided with low-voltage transistors that are more area and power efficient and that are more scalable.

Abstract: A stacked-die image sensor may be provided with an array of image pixels. The stacked-die image sensor may include at least first and second integrated circuit dies stacked on top of one another. Some of the pixel circuitry in each pixel may be formed in the first integrated circuit die and some of the pixel circuitry in each pixel may be formed in the second integrated circuit die. Coupling structures such as conductive pads may electrically couple the pixel circuitry in the first integrated circuit die to the pixel circuitry in the second integrated circuit die. A shielding structure may partially or completely surround each conductive pad to reduce parasitic capacitive coupling between adjacent conductive pads. The shielding structure may be a metal wire coupled to a ground voltage. The shielding structure may extend between columns of image pixels and/or between rows of image pixels.

Abstract: In one embodiment, a method of forming a semiconductor device may include extending a gate conductor of a transistor to overlie a boundary of a well region in which the transistor is formed. The gate conductor may extend to make electrical contact with a gate conductor of a 2nd transistor that is formed external to the well region. A contact conductor may be applied to electrically and physically contact the first and 2nd gate conductors and to also overlie the boundary of the well region.

Abstract: A stacked-die image sensor may be provided with an array of image pixels. The stacked-die image sensor may include at least first and second integrated circuit dies stacked on top of one another. Some of the pixel circuitry in each pixel may be formed in the first integrated circuit die and some of the pixel circuitry in each pixel may be formed in the second integrated circuit die. Coupling structures such as conductive pads may electrically couple the pixel circuitry in the first integrated circuit die to the pixel circuitry in the second integrated circuit die. A shielding structure may partially or completely surround each conductive pad to reduce parasitic capacitive coupling between adjacent conductive pads. The shielding structure may be a metal wire coupled to a ground voltage. The shielding structure may extend between columns of image pixels and/or between rows of image pixels.

Abstract: An image sensor may include an array of pixels, and analog and digital circuitry. The pixels in the array may generate image signals in response to incident light. The image sensor may also include power supply circuitry and corresponding voltage rail structures that provide voltage levels to operate the pixel array, the analog circuitry, and the digital circuitry. The power supply circuitry may provide a low voltage, a high voltage, and an intermediate voltage power rail. The analog circuitry may operate in a voltage level domain defined by voltages between an intermediate voltage level and a high voltage level. The digital circuitry may operate in a voltage level domain defined by voltages between a low voltage level and the intermediate voltage level. In such a configured, analog and digital circuitry may both be provided with low-voltage transistors that are more area and power efficient and that are more scalable.

Abstract: An imaging system may include multi-port pixels. A multi-port pixel may include a photodiode that generates electrical charge in response to received light and a plurality of access ports that couple the electrical charge onto one of a corresponding plurality of pixel output lines. The photodiode may generate electrical charge for one or more different integration times while a frame is being captured. Charge generated during the different integration times may be coupled onto different respective pixel output lines through different respective access ports. Multiple pixels in a given column of the pixel array may simultaneously couple charge generated during different integration times onto different pixel output lines through different access ports.

Abstract: An integrated circuit die may include bottom-gate thin-body transistors. The bottom-gate thin-body transistors may be formed in a thinned-down substrate having a thickness that is defined by shallow trench isolation structures that provide complete well isolation for the transistors. The transistors may include gate terminal contacts formed through the shallow trench isolation structures, bulk terminal contacts that are formed through the thinned substrate and that overlap with the gate contacts, and source-drain terminal contacts with in-situ salicide. Additional metallization layers may be formed over the gate/bulk/source-drain contacts after bonding.

Abstract: A stacked-die image sensor may be provided with an array of image pixels. The stacked-die image sensor may include at least first and second integrated circuit dies stacked on top of one another. Some of the pixel circuitry in each pixel may be formed in the first integrated circuit die and some of the pixel circuitry in each pixel may be formed in the second integrated circuit die. Coupling structures such as conductive pads may electrically couple the pixel circuitry in the first integrated circuit die to the pixel circuitry in the second integrated circuit die. A shielding structure may partially or completely surround each conductive pad to reduce parasitic capacitive coupling between adjacent conductive pads. The shielding structure may be a metal wire coupled to a ground voltage. The shielding structure may extend between columns of image pixels and/or between rows of image pixels.

Abstract: An image sensor with an array of pixels is provided. To minimize optical and electrical and crosstalk, the array of pixels may include deep trench isolation structures interposed between adjacent pairs of photodiodes. In order to maximize quantum efficiency, the array of pixels may include a reflective stack formed under the photodiodes and the deep trench isolation structures. The deep trench isolation structures may be formed from doped glass, doped polysilicon, or metal having a doped oxide liner. The reflective stack may include multiple layers of materials having different indices of refraction. The reflective stack may include oxide, nitride, and semiconductor layers. The deep trench isolation structures may extend from the top of the photodiodes down to the reflective stack. The deep trench isolation structures may have a 50 to 1 aspect ratio.

Abstract: An imaging system may include multi-port pixels. A multi-port pixel may include a photodiode that generates electrical charge in response to received light and a plurality of access ports that couple the electrical charge onto one of a corresponding plurality of pixel output lines. The photodiode may generate electrical charge for one or more different integration times while a frame is being captured. Charge generated during the different integration times may be coupled onto different respective pixel output lines through different respective access ports. Multiple pixels in a given column of the pixel array may simultaneously couple charge generated during different integration times onto different pixel output lines through different access ports.

Abstract: An image sensor with an array of pixels is provided. To minimize optical and electrical and crosstalk, the array of pixels may include deep trench isolation structures interposed between adjacent pairs of photodiodes. In order to maximize quantum efficiency, the array of pixels may include a reflective stack formed under the photodiodes and the deep trench isolation structures. The deep trench isolation structures may be formed from doped glass, doped polysilicon, or metal having a doped oxide liner. The reflective stack may include multiple layers of materials having different indices of refraction. The reflective stack may include oxide, nitride, and semiconductor layers. The deep trench isolation structures may extend from the top of the photodiodes down to the reflective stack. The deep trench isolation structures may have a 50 to 1 aspect ratio.

Abstract: An image sensor with an array of image sensor pixels is provided. The array may be configured to operate in a rolling shutter operation mode or a global shutter operation mode. Each pixel may include body bias control circuitry that generates a body bias control signal. Each pixel may include a photodiode having a p-type terminal that receives the body bias control signal. The body bias control signal may be adjusted to a negative voltage level during the pixel operation to improve the pixel full-well capacity. The body bias control signal may be adjusted to a negative voltage level during reset and charge transfer operations and may be adjusted to a ground voltage level during readout and charge accumulation operations. During rolling shutter operation mode, different body bias control circuits may be used to bias respective rows of pixels within the array.

Abstract: An imaging system may be formed from multiple stacked wafers. A first wafer may include backside illuminated photodiodes, floating diffusion regions, and charge transfer gate structures. The first wafer may be bonded to a second wafer that includes pixel trunk transistors such as reset transistors, source-follower transistors, row-select transistors and associated logic circuits. The pixel trunk transistors may be formed using bottom-gate thin-body transistors. The first and second wafers may share the same backend metallization layers. The second wafer may further be bonded to a third wafer that includes digital signal processing circuits. The digital signal processing circuits may also be implemented using bottom-gate thin-body transistors. Additional metallization layers may be formed over the third wafer. The first, second, and third wafers may be fabricated using the same or different technology nodes.

Abstract: A device having a design conversion from a field programmable gate array (FPGA) to an application specific integrated circuit (ASIC), comprising: a user configurable element in the FPGA replaced by a mask configurable element in the ASIC, wherein the FPGA and the ASIC have identical die size and identical transistor layouts.

Abstract: An image sensor with an array of pixels is provided. In order to achieve high image quality, it may be desirable to improve well capacity of individual pixels within the array. When forming each pixel, multiple n-type compartments having p-type isolation regions interposed between compartments may be formed. These compartments may have higher dopant concentrations due to lateral depletion that may occur within multiple PN-NP back to back junctions to assist full depletion at pinning-voltage. Compartments may allow distributing a moderately higher electric-field over a larger portion of the photodiode while lowering peak electric-fields that contribute to dark-current. Compartments will thereby improve the well capacity of the photodiode while preventing additional noise that may degrade the quality of the image signal. The quantity, doping, and depth of these compartments may be selected to maximize well capacity while minimizing effects on operating voltage, manufacturing cost, and power consumption.

Abstract: An imaging system may be formed from multiple stacked wafers. A first wafer may include backside illuminated photodiodes, floating diffusion regions, and charge transfer gate structures. The first wafer may be bonded to a second wafer that includes pixel trunk transistors such as reset transistors, source-follower transistors, row-select transistors and associated logic circuits. The pixel trunk transistors may be formed using bottom-gate thin-body transistors. The first and second wafers may share the same backend metallization layers. The second wafer may further be bonded to a third wafer that includes digital signal processing circuits. The digital signal processing circuits may also be implemented using bottom-gate thin-body transistors. Additional metallization layers may be formed over the third wafer. The first, second, and third wafers may be fabricated using the same or different technology nodes.

Abstract: An integrated circuit die may include bottom-gate thin-body transistors. The bottom-gate thin-body transistors may be formed in a thinned-down substrate having a thickness that is defined by shallow trench isolation structures that provide complete well isolation for the transistors. The transistors may include gate terminal contacts formed through the shallow trench isolation structures, bulk terminal contacts that are formed through the thinned substrate and that overlap with the gate contacts, and source-drain terminal contacts with in-situ salicide. Additional metallization layers may be formed over the gate/bulk/source-drain contacts after bonding.

Abstract: An image sensor with an array of pixels is provided. In order to achieve high image quality, it may be desirable to improve well capacity of individual pixels within the array. When forming each pixel, multiple n-type compartments having p-type isolation regions interposed between compartments may be formed. These compartments may have higher dopant concentrations due to lateral depletion that may occur within multiple PN-NP back to back junctions to assist full depletion at pinning-voltage. Compartments may allow distributing a moderately higher electric-field over a larger portion of the photodiode while lowering peak electric-fields that contribute to dark-current. Compartments will thereby improve the well capacity of the photodiode while preventing additional noise that may degrade the quality of the image signal. The quantity, doping, and depth of these compartments may be selected to maximize well capacity while minimizing effects on operating voltage, manufacturing cost, and power consumption.