Abstract: The disclosure describes devices and methods for starting up a microphone assembly. The device may be implemented on an integrated circuit that includes a direct current (DC) bias circuit. The DC bias circuit may be coupled to a transducer and configured to supply a DC bias signal to the transducer. The DC bias circuit includes a multi-stage charge pump and a low pass filter (LPF) circuit. The LPF circuit includes an adjustable resistance and a capacitor. A resistance of the adjustable resistance may be reduced to reduce the settling time of the LPF while starting (e.g., turning on) the microphone assembly.

Abstract: The disclosure describes devices and methods for starting up a microphone assembly. The device may be implemented on an integrated circuit that includes a direct current (DC) bias circuit. The DC bias circuit may be coupled to a transducer and configured to supply a DC bias signal to the transducer. The DC bias circuit includes a multi-stage charge pump and a low pass filter (LPF) circuit. The LPF circuit includes an adjustable resistance and a capacitor. A resistance of the adjustable resistance may be reduced to reduce the settling time of the LPF while starting (e.g., turning on) the microphone assembly.

Abstract: A circuit and method for signal amplification is provided. The circuit includes an amplifier including an input amplifier that is arranged to receive an input analog signal, and to provide an input amplifier output signal by amplifying the input analog signal. The amplifier further includes a DC offset correction circuit that is arranged to determine a DC offset correction for the input amplifier each time the amplifier is powered up. The DC offset correction is performed by iteratively adjusting a DC offset of the input amplifier until the input amplifier output DC offset is zero when the input analog AC signal is zero, within a predetermined tolerance. The DC offset correction circuit is further arranged to provide the determined DC offset correction to the input amplifier during operation of the amplifier.

Abstract: An apparatus includes first and second amplifiers, each having an input coupled to an audio signal input and an output coupled to an audio signal output. The second amplifier also has a feedback path from its output to its input. A first switch can be operated to selectively couple and uncouple the audio signal input and the input to the first amplifier to and from a first node. A second switch can be operated to selectively couple and uncouple the input of the second amplifier to and from a second node. A third switch can be operated to selectively couple and uncouple the first node to and from ground.

Abstract: An input stage for an audio power amplifier is provided. The input stage includes a fully differential amplifier and a supply-independent reference voltage generator. The supply-independent reference voltage generator provides a supply-independent reference voltage that is used as the common mode voltage of the output of the fully differential amplifier.

Abstract: An audio amplifier with an integrated asymmetric charge pump is provided. The audio amplifier receives VDD and VSS as power supply signals. The integrated charge pump is arranged to provide VSS from VDD, such that VSS is a negative voltage that is lower in magnitude than VDD.

Abstract: A fully differential class D amplifier is provided. The class D amplifier includes an active amplifier in the feedback path of the modulator. In one embodiment, the class D amplifier includes a fully differential amplifier as an input buffer, in which a supply-independent reference voltage is used as the common mode voltage of the output of the fully differential amplifier. In one embodiment, the class D amplifier includes a pulse width modulation circuit that includes rail-to-rail comparators.

Abstract: An audio amplifier with an integrated asymmetric charge pump is provided. The audio amplifier receives VDD and VSS as power supply signals. The integrated charge pump is arranged to provide VSS from VDD, such that VSS is a negative voltage that is lower in magnitude than VDD.

Abstract: A timer circuit that has a normal mode and a test mode is disclosed. The test mode includes a power-up phase and a power-down phase. The timer circuit includes an oscillator and a first timer circuit portion coupled to the oscillator. The first timer circuit portion includes an input and an output. An output signal that confirms either the satisfactory or unsatisfactory operation of the first timer circuit portion is taken from the output associated with the first timer circuit portion in the power-up phase. The timer circuit further includes a second timer circuit portion coupled to the first timer circuit portion and the oscillator. The second timer circuit portion also includes an input and an output. An output signal that confirms either the satisfactory or unsatisfactory operation of the second timer circuit portion is taken from the output associated with the second timer circuit portion in the power-down phase.

Abstract: A circuit for audio amplification includes an amplifier and a first input resistor. The amplifier is arranged to provide an amplifier output signal that is based, in part, on a capacitively-coupled audio input signal. The capacitively-coupled audio input signal is based, in part, on an input RC value. The input RC value is given by the input capacitance times the input resistance. The input resistance is reduced during the turn-on in order to achieve a fast turn-on time with minimal pop-and-click noise. Also, the input resistance is increased to its normal value after the turn-on so that full audio fidelity is substantially maintained during normal operation.

Abstract: A low current differential fuse circuit for adjusting the operating characteristics of semiconductor circuits. A switching circuit is connected between a first and a second fuse. The first and second fuses are respectively connected to a supply potential (e.g., 5.0 volts) and a reference potential (e.g., 0.0 volts). Additionally, each fuse is connected to a circuit for blowing the fuse. The switching circuit is also connected to a bias circuit that biases the switching components (e.g., a PMOS transistor and an NMOS transistor) to ensure that the switching circuit correctly switches in response to a selected fuse (e.g., either the first fuse or the second fuse) being blown (e.g., opened). An inverter circuit may also be provided between a switching node and an output node to provide a desired output potential.