Abstract: A transceiver for communicating a multi-tone modulated communication channel on a subscriber line. The transceiver includes: a digital signal processor (DSP) with a Fourier transform module and an analog front end (AFE). The DSP determines an available range of frequencies on the subscriber line and expands or contracts the tone spacing of each of a fixed number “N” of tones accordingly by decreasing or increasing the processing interval associated with the Fourier transform of each tone set. The AFE performs digital-to-analog conversion of the multi-tone modulated communication channel at rates compatible with the processing interval of the Fourier transform module; whereby the range of frequencies spanned by the modulated tones on the subscriber line conforms to the available of frequencies on the subscriber line.

Abstract: The current invention provides a method and apparatus for time domain equalization in an XDSL modem. A received communication channel is analyzed to determine the highest frequency component thereof. Typically, there is an inverse relationship between the length of a subscriber line and the highest frequency component over which communications can be supported. In response to the frequency determination, the sampling rate for the channel is reduced to the lowest sample rate consistent with maintaining signal integrity on the highest frequency component of the channel. The sampling rate reduction may accomplished in the analog portion of the receive path, e.g. the analog-to-digital converter (ADC) or in a digital decimator coupled thereto. Concurrently the demodulator complexity is also scaled back. Where the XDSL protocol is digital multi-tone (DMT) the input sample size to the discrete Fourier transform (DFT) engine is reduced accordingly.

Abstract: A Fourier transform processor utilizing discrete circuits each of which is configurable for processing a wide range of sample sizes. A single pipeline supports multiplexed bi-directional transformations between for example the time and frequency domains. In an embodiment of the invention the Fourier Transform processor may be implemented as part of a digital signal processor (DSP). In this embodiment the DSP may implement both the discrete Fourier transform (DFT) and inverse discrete Fourier transform (IDFT) across a wide range of sample sizes and X-DSL protocols. Multiple channels, each with varying ones of the X-DSL protocols can be handled in the same session.

Abstract: The current invention provides a DSP which accommodates multiple current X-DSL protocols and is further configurable to support future protocols. The DSP is implemented with shared and dedicated hardware components on both the transmit and receive paths. The DSP implements both the discrete Fourier transform (DFT) and inverse discrete Fourier transform (IDFT) portions across a wide range of sample sizes and X-DSL protocols. Multiple channels, each with varying ones of the X-DSL protocols can be handled in the same session. The DSP offers the speed associated with hardware implementation of the transforms and the flexibility of a software only implementation. Traffic flow is regulated in the chip using a packet based schema in which each packet is associated with a specific channel of upstream and downstream data. Header and control information in each packet is used to govern the processing of each packet as it moves along either the transmit path or receive path.

Abstract: The current invention provides a digital signal processor which supports multiple X-DSL protocols and a multiplicity of channels on a single chip. Each channel is packetized and each packet includes control information for controlling the performance of the components/modules on the transmit and receive path. Further flexibility is derived from an architecture which incorporates discrete and shared modules on the transmit path and the receive path. The transmit path and receive path modules are collectively controlled by control information in selected ones of the packets and operate on each channel's packets at an appropriate rate, and protocol for the channel. A digital signal processor (DSP) is disclosed which incorporates these features. The DSP exhibits a favorable form factor, and flexibility as to protocols and line codes, and numbers of channels supported.