Abstract: An information transfer system is described that includes a central processing unit (CPU) interconnected with a peripheral device such as an operator console by an interface bus of finite capacity. Transfer of information in the system is normally in a preferred direction from the CPU to the console. Provision is made to transfer information concerning key depressions on the console from the console to the CPU without using the bus by utilizing a normally continuously operating counter in the CPU that provides a sequence of coded count signals representative of individual keys that are provided on the console and that may be depressed. A comparator in the console compares coded count signals from the CPU counter with coded signals from the console representative of actual key depressions and provides a stop signal to the CPU counter via a single control line when an equal compare of the CPU counter and console coded signals occurs.