Abstract: A beauty tool includes a handle portion configured to house an associated heating assembly and a bristle portion connected to the handle portion. The bristle portion includes a primary heating element configured to be heated by the associated heating assembly. A bristle base heated member is mounted to an outer periphery of the heating element. The bristle base heated member has a secondary heating element configured to be heated by the primary heating element. A non-conductive, heat insulating bristle spacer is secured between the bristle base heated member and the heating element. A bristle bar is secured by the bristle spacer and has bristles extending through the bristle spacer and the bristle base heated member. The bristle spacer is configured to thermally isolate the bristle bar from both the heating element and the bristle base heated member.

Abstract: A semiconductor device is manufactured using an ashing process to eliminate the adverse effects of contamination, such as amine-airborne contamination. Consistent with one embodiment of the present invention, the semiconductor device is formed by applying a DUV-type photoresist over the wafer surface, exposing the photoresist to DUV light, baking the wafer, and then ashing the wafer in a highly-oxidized environment to remove insoluble amine-related resist.

Abstract: The present invention is a method of suppressing etchrate of quartz hardware in semiconductor processing chamber during plasma-enhanced cleaning. In one embodiment, the method of the present invention includes the steps of: (a) introducing a mixture of fluorocarbon gas, oxygen, and water vapor into the chamber; and (b) activating the mixture to form a quartz-safe plasma cleaning gas. According to the present invention, the presence of water vapor substantially suppresses etching of quartz hardware. Etchrate of the polymer contaminants, however, is substantially unaffected. In one embodiment of the invention, the fluorocarbon gas includes CF4, and, water vapor is introduced at a rate of at least 60 standard cubic centimeters per minute (SCCM).

Abstract: Disclosed are techniques to provide an integrated circuit, including the provision of improved integrated circuit isolation structures. The techniques include forming a number of trenches in an integrated circuit substrate to define a number of substrate regions that are to be electrically isolated from one another. A dielectric material is deposited in the trenches by exposure to a high density plasma having a first deposition-to-etch ratio. The high density plasma is adjusted to a second deposition-to-etch ratio greater than the first ratio to accumulate the dielectric material on the substrate after at least partially filling the trenches. A portion of the dielectric material is removed to planarize the workpiece. A number of components, such as insulated gate field effect transistors, may be subsequently formed in the substrate regions between the trenches.

Abstract: The present invention is a method of suppressing etchrate of quartz hardware in semiconductor processing chamber during plasma-enhanced cleaning. In one embodiment, the method of the present invention comprises the steps of: (a) introducing a mixture of fluorocarbon gas, oxygen, and water vapor into the chamber; and (b) activating the mixture to form a quartz-safe plasma cleaning gas. According to the present invention, the presence of water vapor substantially suppresses etching of quartz hardware. Etchrate of the polymer contaminants, however, is substantially unaffected. In one embodiment of the invention, the fluorocarbon gas comprises CF4, and, water vapor is introduced at a rate of at least 60 standard cubic centimeters per minute (SCCM).

Abstract: A method of plasma etching photoresist and sidewall polymer with an etch gas mixture comprising a fluorine containing gas (CF.sub.4 or NF.sub.3) and H.sub.2 O demonstrating very aggressive ashrate of photoresist but maintains an exceptionally low etch rate for titanium nitride and other metals is provided. The very low TiN etch rate permits the inventive method to effectively breakdown sidewall polymer without removing any significant amount of these metals. The invention is particularly suited for stripping sidewall polymer from etched via holes and from etched metal lines. Vias fabricated with this technique exhibit exceptionally low resistance.

Abstract: A method for preparing a semiconductor substrate and a polysilicon gate for subsequent silicide formation. In one embodiment, the present invention performs an oxide etch to remove oxide from source and drain diffusion regions of the semiconductor substrate and from the top surface of the polysilicon gate. Next, the present invention subjects the semiconductor substrate and the polysilicon gate to an ashing environment. In the present invention, the ashing environment is comprised of H.sub.2 O vapor, and a gaseous fluorocarbon or a fluorinated hydrocarbon gas. In so doing, contaminants introduced into the source and drain diffusion regions of the semiconductor substrate and into the top surface of the polysilicon gate during the oxide etch are removed. Next, the present invention performs a semiconductor wafer surface clean step. The semiconductor wafer surface clean step provides a semiconductor wafer surface which is substantially similar to a virgin silicon surface.

Abstract: A method of plasma etching photoresist and sidewall polymer with an etch gas mixture comprising CF.sub.4 and H.sub.2 O demonstrating very aggressive ashrate of photoresist but maintains an exceptionally low etch rate for titanium nitride and other metals is provided. The very low TiN etch rate permits the inventive method to effectively breakdown sidewall polymer without removing any significant amount of these metals. The invention is particularly suited for stripping sidewall polymer from etched via holes and from etched metal lines.

Abstract: A method for enhancing sidewall polymer removal. In one embodiment of the present invention, O.sub.2 is introduced into an ashing environment at a flow rate of approximately 800 standard cubic centimeters per minute (SCCM). In the present embodiment, CF.sub.4 is also introduced into the ashing environment. The CF.sub.4 is introduced at a flow rate of approximately 80 SCCM. The ashing environment also has H.sub.2 O vapor introduced therein. In the present embodiment, the H.sub.2 O vapor is introduced into the ashing environment at a flow rate of approximately 80 SCCM. The ashing environment is used to selectively etch sidewall polymer material, thereby providing a method for removing sidewall polymer material without detrimentally etching other materials.

Abstract: A system for evacuating a reactor chamber includes a main evacuation line connected at one end thereof to the reactor chamber and at another end thereof to a means for creating a partial vacuum. A valve in the main evacuation line divides the line into a chamber side and a vacuum side. A second line is connected at one end to the vacuum side of the main evacuation line and at another end to a fluid supply source. As the valve in the main evacuation line is opened, fluid is supplied through the second line to the main evacuation line to prevent rapid, turbulence-inducing pressure drops in the reactor chamber.