Patents by Inventor Ramkumar Nagappan
Ramkumar Nagappan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11650652Abstract: Apparatus, systems, and methods provide an interface between a plurality of hardware resources of a node and a power manager. The interface is configured to define one or more resource groups to expose to the power manager for power measurement and control, assign the plurality of hardware resources to the one or more resource groups, and provide a power allowance to each resource group.Type: GrantFiled: June 24, 2021Date of Patent: May 16, 2023Assignee: INTEL CORPORATIONInventors: Federico Ardanaz, Jonathan M. Eastep, Richard J. Greco, Ramkumar Nagappan, Alan B. Kyker
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Publication number: 20210325952Abstract: Apparatus, systems, and methods provide an interface between a plurality of hardware resources of a node and a power manager. The interface is configured to define one or more resource groups to expose to the power manager for power measurement and control, assign the plurality of hardware resources to the one or more resource groups, and provide a power allowance to each resource group.Type: ApplicationFiled: June 24, 2021Publication date: October 21, 2021Applicant: INTEL CORPORATIONInventors: Federico Ardanaz, Jonathan M. Eastep, Richard J. Greco, Ramkumar Nagappan, Alan B. Kyker
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Patent number: 11061463Abstract: Apparatus, systems, and methods provide an interface between a plurality of hardware resources of a node and a power manager. The interface is configured to define one or more resource groups to expose to the power manager for power measurement and control, assign the plurality of hardware resources to the one or more resource groups, and provide a power allowance to each resource group.Type: GrantFiled: August 29, 2017Date of Patent: July 13, 2021Assignee: Intel CorporationInventors: Federico Ardanaz, Jonathan M. Eastep, Richard J. Greco, Ramkumar Nagappan, Alan B. Kyker
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Publication number: 20210191490Abstract: Methods and apparatus for balancing power between discrete components, such as processing units (e.g., CPUs) and accelerators in a compute node or platform. Power consumption of the compute platform is monitored to detect for conditions under which a threshold (e.g., power supply capacity threshold) is exceeded. In response, the operating frequencies of a processing unit and/or other platform components such as accelerators, are adjusted to reduce the power consumption of the platform to return below the threshold. Power limit biasing hints (scaling weights) are provided to platform components, along with a power violation index, which are used to adjust the operating frequencies of the platform components. Optionally, a processing unit can calculate the power violation index and the scaling weights and directly control the frequencies of itself and platform components. Embodiments of multi-socket platforms are also provided.Type: ApplicationFiled: March 3, 2021Publication date: June 24, 2021Inventors: Phani Kumar KANDULA, Eric J. DEHAEMER, Dorit SHAPIRA, Ramkumar NAGAPPAN, Vivek GARG, Fuat KECELI, Mani PRAKASH, David C. HOLCOMB, Horthense D. TAMDEM, Olivier FRANZA, Vjekoslav SVILAN
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Patent number: 10612980Abstract: An apparatus is provided which comprises: a first circuitry to receive a measurement of a first temperature of a section of a computing device during a first loading condition of the computing device, and to receive a measurement of a second temperature of the section of the computing device during a second loading condition of the computing device; and a second circuitry to detect a potential fault in a cooling system to cool the computing device, based at least in part on the first temperature and the second temperature.Type: GrantFiled: June 21, 2017Date of Patent: April 7, 2020Assignee: Intel CorporationInventors: Janusz P. Jurski, Tozer J. Bandorawalla, Ramkumar Nagappan, Mariusz Oriol, Piotr Sawicki, Robin A. Steinbrecher, Shankar Krishnan
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Patent number: 10355959Abstract: Examples are disclosed for determining or using server transaction latency information. In some examples, a network input/output device coupled to a server may be capable of time stamping information related to ingress request and egress response packets for a transaction. For these examples, elements of the server may be capable of determining transaction latency values based on the time stamped information. The determined transaction latency values may be used to monitor or manage operating characteristics of the server to include an amount of power provided to the server or an ability of the server to support one or more virtual servers. Other examples are described and claimed.Type: GrantFiled: November 21, 2016Date of Patent: July 16, 2019Assignee: INTEL CORPORATIONInventors: Manasi Deval, Jim Daubert, Eric K. Mann, Cong Li, Muralidhar Murali Rajappa, Anjaneya Reddy Chagam Reddy, David Wescott, Ramkumar Nagappan, Raed Kanjo
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Publication number: 20180372551Abstract: An apparatus is provided which comprises: a first circuitry to receive a measurement of a first temperature of a section of a computing device during a first loading condition of the computing device, and to receive a measurement of a second temperature of the section of the computing device during a second loading condition of the computing device; and a second circuitry to detect a potential fault in a cooling system to cool the computing device, based at least in part on the first temperature and the second temperature.Type: ApplicationFiled: June 21, 2017Publication date: December 27, 2018Inventors: Janusz P. Jurski, Tozer J. Bandorawalla, Ramkumar Nagappan, Mariusz Oriol, Piotr Sawicki, Robin A. Steinbrecher, Shankar Krishnan
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Publication number: 20180067533Abstract: Apparatus, systems, and methods provide an interface between a plurality of hardware resources of a node and a power manager. The interface is configured to define one or more resource groups to expose to the power manager for power measurement and control, assign the plurality of hardware resources to the one or more resource groups, and provide a power allowance to each resource group.Type: ApplicationFiled: August 29, 2017Publication date: March 8, 2018Applicant: INTEL CORPORATIONInventors: Federico Ardanaz, Jonathan M. Eastep, Richard J. Greco, Ramkumar Nagappan, Alan B. Kyker
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Patent number: 9864423Abstract: Apparatus and methods may provide for characterizing a plurality of similar components of a distributed computing system based on a maximum safe operation level associated with each component and storing characterization data in a database and allocating non-uniform power to each similar component based at least in part on the characterization data in the database to substantially equalize performance of the components.Type: GrantFiled: December 24, 2015Date of Patent: January 9, 2018Assignee: Intel CorporationInventors: Alan G. Gara, Steve S. Sylvester, Jonathan M. Eastep, Ramkumar Nagappan, Christopher M. Cantalupo
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Patent number: 9753526Abstract: Apparatus, systems, and methods provide an interface between a plurality of hardware resources of a node and a power manager. The interface is configured to define one or more resource groups to expose to the power manager for power measurement and control, assign the plurality of hardware resources to the one or more resource groups, and provide a power allowance to each resource group.Type: GrantFiled: December 23, 2014Date of Patent: September 5, 2017Assignee: INTEL CORPORATIONInventors: Federico Ardanaz, Jonathan M. Eastep, Richard J. Greco, Ramkumar Nagappan, Alan B. Kyker
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Publication number: 20170201448Abstract: Examples are disclosed for determining or using server transaction latency information. In some examples, a network input/output device coupled to a server may be capable of time stamping information related to ingress request and egress response packets for a transaction. For these examples, elements of the server may be capable of determining transaction latency values based on the time stamped information. The determined transaction latency values may be used to monitor or manage operating characteristics of the server to include an amount of power provided to the server or an ability of the server to support one or more virtual servers. Other examples are described and claimed.Type: ApplicationFiled: November 21, 2016Publication date: July 13, 2017Applicant: INTEL CORPORATIONInventors: MANASI DEVAL, JIM DAUBERT, ERIC K. MANN, CONG LI, MURALIDHAR RAJAPPA, ANJANEYA REDDY CHAGAM REDDY, DAVID WESCOTT, RAMKUMAR NAGAPPAN, RAED KANJO
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Publication number: 20170185129Abstract: Apparatus and methods may provide for characterizing a plurality of similar components of a distributed computing system based on a maximum safe operation level associated with each component and storing characterization data in a database and allocating non-uniform power to each similar component based at least in part on the characterization data in the database to substantially equalize performance of the components.Type: ApplicationFiled: December 24, 2015Publication date: June 29, 2017Applicant: Intel CorporationInventors: Alan G. Gara, Steve S. Sylvester, Jonathan M. Eastep, Ramkumar Nagappan, Christopher M. Cantalupo
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Patent number: 9503347Abstract: Examples are disclosed for determining or using server transaction latency information. In some examples, a network input/output device coupled to a server may be capable of time stamping information related to ingress request and egress response packets for a transaction. For these examples, elements of the server may be capable of determining transaction latency values based on the time stamped information. The determined transaction latency values may be used to monitor or manage operating characteristics of the server to include an amount of power provided to the server or an ability of the server to support one or more virtual servers. Other examples are described and claimed.Type: GrantFiled: December 18, 2012Date of Patent: November 22, 2016Assignee: INTEL CORPORATIONInventors: Manasi Deval, Jim Daubert, Eric Mann, Cong Li, Muralidhar Murali Rajappa, Anjaneya Reddy Chagam Reddy, David Wescott, Ramkumar Nagappan, Raed Kanjo
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Publication number: 20160179157Abstract: Apparatus, systems, and methods provide an interface between a plurality of hardware resources of a node and a power manager. The interface is configured to define one or more resource groups to expose to the power manager for power measurement and control, assign the plurality of hardware resources to the one or more resource groups, and provide a power allowance to each resource group.Type: ApplicationFiled: December 23, 2014Publication date: June 23, 2016Applicant: Intel CorporationInventors: FEDERICO ARDANAZ, JONATHAN M. EASTEP, RICHARD J. GRECO, RAMKUMAR NAGAPPAN, ALAN B. KYKER
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Patent number: 9195404Abstract: Mechanisms for exposing a protected memory address are provided. A processing device may store a data value at a protected memory address. The protected memory address may be a control register or a status register. The processing device may identify a mirror relationship between the protected memory address and an unprotected memory address and copy the data value from the protected memory address to the unprotected memory address. The unprotected memory address may be directly accessible via an external interface.Type: GrantFiled: December 17, 2013Date of Patent: November 24, 2015Assignee: Intel CorporationInventors: James W. Alexander, Devadatta V. Bodas, Muralidhar Rajappa, Ramkumar Nagappan, Andy Hoffman
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Publication number: 20150222516Abstract: Examples are disclosed for determining or using server transaction latency information. In some examples, a network input/output device coupled to a server may be capable of time stamping information related to ingress request and egress response packets for a transaction. For these examples, elements of the server may be capable of determining transaction latency values based on the time stamped information. The determined transaction latency values may be used to monitor or manage operating characteristics of the server to include an amount of power provided to the server or an ability of the server to support one or more virtual servers. Other examples are described and claimed.Type: ApplicationFiled: December 18, 2012Publication date: August 6, 2015Inventors: Manasi Deval, Jim Daubert, Eric Mann, Cong Li, Muralidhar Murali Rajappa, Anjaneya Reddy Chagam Reddy, David Wescott, Ramkumar Nagappan, Raed Kanjo
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Publication number: 20150169224Abstract: Mechanisms for exposing a protected memory address are provided. A processing device may store a data value at a protected memory address. The protected memory address may be a control register or a status register. The processing device may identify a mirror relationship between the protected memory address and an unprotected memory address and copy the data value from the protected memory address to the unprotected memory address. The unprotected memory address may be directly accessible via an external interface.Type: ApplicationFiled: December 17, 2013Publication date: June 18, 2015Inventors: James W. Alexander, Devadatta V. Bodas, Muralidhar Rajappa, Ramkumar Nagappan, Andy Hoffman