Patents by Inventor Ramkumar Ramamurthy

Ramkumar Ramamurthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11849186
    Abstract: A data storage device and method for enabling metadata-based seek points for media access are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to identify a plurality of frames in video data that differ from surrounding frames by more than a threshold amount; store identifiers of the plurality of frames in the memory; and send the identifiers to the host to enable quick playback of the video data by the host. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: December 19, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ramkumar Ramamurthy, Ramanathan Muthiah
  • Publication number: 20230403433
    Abstract: A data storage device and method for enabling metadata-based seek points for media access are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to identify a plurality , of frames in video data that differ from surrounding frames by more than a threshold amount; store identifiers of the plurality of frames in the memory; and send the identifiers to the host to enable quick playback of the video data by the host. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
    Type: Application
    Filed: June 14, 2022
    Publication date: December 14, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Ramkumar Ramamurthy, Ramanathan Muthiah
  • Patent number: 11775210
    Abstract: A storage system and method for device-determined, application-specific dynamic command clustering are provided. In one embodiment, the storage system comprises a memory and a controller. The controller is configured to analyze commands received from a host to detect a pattern of a plurality of commands; inform the host of the pattern; receive, from the host, a single command comprising an identifier associated with the plurality of commands; and in response to receiving the single command from the host, executing the plurality of commands. Other embodiments are provided.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: October 3, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ramanathan Muthiah, Narendhiran Chinnaanangur Ravimohan, Balaji Thraksha Venkataramanan, Ramkumar Ramamurthy
  • Patent number: 11681466
    Abstract: Example storage systems, storage devices, and methods provide proactive management of storage operations to, for example, beneficially minimize bottlenecking, latency, and other issues. An example system has a storage pool with a first storage device and a second storage device, and a processor configured to generate a storage request including a storage command, include a command processing time constraint in the storage request, send the storage request to the first storage device, and receive, from the first storage device, a proactive response including an estimation for an execution of the storage command by the first storage device based on the command processing time constraint. The processor may then select a fallback mechanism for executing the storage command based on the proactive response.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: June 20, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ramanathan Muthiah, Ramkumar Ramamurthy
  • Publication number: 20220138545
    Abstract: Various embodiments of this disclosure are directed to a mixed digital and analog domain approach to computational storage or memory applications. The mixed approach enables certain compute operations to be advantageously performed in the analog domain, achieving power saving. In some embodiments, an analog compute core is implemented based on a first set of memory elements that are made available with a second set of memory elements for digital data storage. A controller coupled to both sets of memory elements is able to selectively direct computational tasks to either the analog compute core or a digital processor coupled with the controller, based on one or more parameters including power, precision, and workload. In certain embodiments involving neural network tasks, the controller is configured to route certain tasks to the analog compute core based on neural network based factors such as network layer positioning and input signal type.
    Type: Application
    Filed: February 11, 2021
    Publication date: May 5, 2022
    Inventors: Ramanathan Muthiah, Ramkumar Ramamurthy
  • Publication number: 20220113904
    Abstract: A storage system and method for device-determined, application-specific dynamic command clustering are provided. In one embodiment, the storage system comprises a memory and a controller. The controller is configured to analyze commands received from a host to detect a pattern of a plurality of commands; inform the host of the pattern; receive, from the host, a single command comprising an identifier associated with the plurality of commands; and in response to receiving the single command from the host, executing the plurality of commands. Other embodiments are provided.
    Type: Application
    Filed: February 17, 2021
    Publication date: April 14, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Ramanathan Muthiah, Narendhiran Chinnaanangur Ravimohan, Balaji Thraksha Venkataramanan, Ramkumar Ramamurthy
  • Publication number: 20210405924
    Abstract: Example storage systems, storage devices, and methods provide proactive management of storage operations to, for example, beneficially minimize bottlenecking, latency, and other issues. An example system has a storage pool with a first storage device and a second storage device, and a processor configured to generate a storage request including a storage command, include a command processing time constraint in the storage request, send the storage request to the first storage device, and receive, from the first storage device, a proactive response including an estimation for an execution of the storage command by the first storage device based on the command processing time constraint. The processor may then select a fallback mechanism for executing the storage command based on the proactive response.
    Type: Application
    Filed: June 30, 2020
    Publication date: December 30, 2021
    Inventors: Ramanathan Muthiah, Ramkumar Ramamurthy
  • Patent number: 11036411
    Abstract: Apparatuses and techniques are described for more efficiently allocating blocks of data in a memory device. The number of dedicated single-level cell (SLC) blocks which are allocated at the time of manufacture of a memory device can be reduced by transitioning a portion of the multi-level cell (MLC) blocks to an SLC mode at various times in the lifetime of the memory device. In one approach, separate counts are maintained for an MLC block in the SLC and MLC modes. The separate counts can be used to select an MLC block to transition to the SLC mode, or to select an MLC block to program. In another approach, a single count is maintained, where the SLC cycles are weighted less heavily than the MLC cycles.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: June 15, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Narendhiran Chinnaanangur Ravimohan, Muralitharan Jayaraman, Arun Thandapani, Ramkumar Ramamurthy
  • Patent number: 11030106
    Abstract: A storage system and method for enabling host-driven regional performance in memory are provided. In one embodiment, a method is provided comprising receiving a directive from a host device as to a preferred logical region of a non-volatile memory in a storage system; and based on the directive, modifying a caching policy specifying which pages of a logical-to-physical address map stored in the non-volatile memory are to be cached in a volatile memory of the storage system. Other embodiments are provided, such as modifying a garbage collection policy of the storage system based on information from the host device regarding a preferred logical region of the memory.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: June 8, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ramanathan Muthiah, Ramkumar Ramamurthy, Judah Gamliel Hahn
  • Patent number: 11010057
    Abstract: A storage system, host, and method for storage system calibration are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to: determine a pattern of host writes to the memory; determine whether the pattern of host writes matches a granularity of a logical-to-physical address map used by the storage system; and in response to determining that the pattern of host writes does not match the granularity of the logical-to-physical address map used by the storage system, change the granularity of the logical-to-physical address map used by the storage system. In another embodiment, the storage system calibration is done by host directive. Other embodiments are provided.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: May 18, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ramanathan Muthiah, Ramkumar Ramamurthy
  • Patent number: 10997081
    Abstract: A storage system, host, and method for storage system calibration are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to: determine a pattern of host writes to the memory; determine whether the pattern of host writes matches a granularity of a logical-to-physical address map used by the storage system; and in response to determining that the pattern of host writes does not match the granularity of the logical-to-physical address map used by the storage system, change the granularity of the logical-to-physical address map used by the storage system. In another embodiment, the storage system calibration is done by host directive. Other embodiments are provided.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: May 4, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ramanathan Muthiah, Ramkumar Ramamurthy
  • Patent number: 10901912
    Abstract: An apparatus is provided that includes a non-volatile memory and a memory controller coupled to the non-volatile memory. The memory controller is configured to access a global address table (GAT) that maps logical addresses of a host to physical addresses of the non-volatile memory, receive a request from the host to write first data to the non-volatile memory, determine that the first data comprises fragmented data that are not aligned to a minimum write unit of the non-volatile memory, and create an unaligned GAT page, wherein the unaligned GAT page comprises a logical-to-physical mapping for the first data.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: January 26, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ramkumar Ramamurthy, Ramanathan Muthiah
  • Publication number: 20200401525
    Abstract: A storage system and method for enabling host-driven regional performance in memory are provided. In one embodiment, a method is provided comprising receiving a directive from a host device as to a preferred logical region of a non-volatile memory in a storage system; and based on the directive, modifying a caching policy specifying which pages of a logical-to-physical address map stored in the non-volatile memory are to be cached in a volatile memory of the storage system. Other embodiments are provided, such as modifying a garbage collection policy of the storage system based on information from the host device regarding a preferred logical region of the memory.
    Type: Application
    Filed: June 18, 2019
    Publication date: December 24, 2020
    Applicant: Western Digital Technologies, Inc.
    Inventors: Ramanathan Muthiah, Ramkumar Ramamurthy, Judah Gamliel Hahn
  • Publication number: 20200401332
    Abstract: Apparatuses and techniques are described for more efficiently allocating blocks of data in a memory device. The number of dedicated single-level cell (SLC) blocks which are allocated at the time of manufacture of a memory device can be reduced by transitioning a portion of the multi-level cell (MLC) blocks to an SLC mode at various times in the lifetime of the memory device. In one approach, separate counts are maintained for an MLC block in the SLC and MLC modes. The separate counts can be used to select an MLC block to transition to the SLC mode, or to select an MLC block to program. In another approach, a single count is maintained, where the SLC cycles are weighted less heavily than the MLC cycles.
    Type: Application
    Filed: June 24, 2019
    Publication date: December 24, 2020
    Applicant: Western Digital Technologies, Inc.
    Inventors: Narendhiran Chinnaanangur Ravimohan, Muralitharan Jayaraman, Arun Thandapani, Ramkumar Ramamurthy
  • Publication number: 20200379910
    Abstract: A storage system, host, and method for storage system calibration are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to: determine a pattern of host writes to the memory; determine whether the pattern of host writes matches a granularity of a logical-to-physical address map used by the storage system; and in response to determining that the pattern of host writes does not match the granularity of the logical-to-physical address map used by the storage system, change the granularity of the logical-to-physical address map used by the storage system. In another embodiment, the storage system calibration is done by host directive. Other embodiments are provided.
    Type: Application
    Filed: May 29, 2019
    Publication date: December 3, 2020
    Applicant: Western Digital Technologies, Inc.
    Inventors: Ramanathan Muthiah, Ramkumar Ramamurthy
  • Publication number: 20200379643
    Abstract: A storage system, host, and method for storage system calibration are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to: determine a pattern of host writes to the memory; determine whether the pattern of host writes matches a granularity of a logical-to-physical address map used by the storage system; and in response to determining that the pattern of host writes does not match the granularity of the logical-to-physical address map used by the storage system, change the granularity of the logical-to-physical address map used by the storage system. In another embodiment, the storage system calibration is done by host directive. Other embodiments are provided.
    Type: Application
    Filed: May 29, 2019
    Publication date: December 3, 2020
    Applicant: Western Digital Technologies, Inc.
    Inventors: Ramanathan Muthiah, Ramkumar Ramamurthy
  • Publication number: 20200242045
    Abstract: An apparatus is provided that includes a non-volatile memory and a memory controller coupled to the non-volatile memory. The memory controller is configured to access a global address table (GAT) that maps logical addresses of a host to physical addresses of the non-volatile memory, receive a request from the host to write first data to the non-volatile memory, determine that the first data comprises fragmented data that are not aligned to a minimum write unit of the non-volatile memory, and create an unaligned GAT page, wherein the unaligned GAT page comprises a logical-to-physical mapping for the first data.
    Type: Application
    Filed: January 28, 2019
    Publication date: July 30, 2020
    Applicant: Western Digital Technologies, Inc.
    Inventors: Ramkumar Ramamurthy, Ramanathan Muthiah
  • Publication number: 20200226064
    Abstract: A method for data consolidation in a memory system includes selecting a source block for data consolidation from a plurality of memory blocks in the memory system. The method further includes reading a physical-to-logical address mapping table associated with the source block to determine a first logical group in the source block. The method further includes loading a first logical-to-physical address mapping table associated with the first logical group. The method further includes identifying, using the first logical-to-physical address mapping table, valid memory fragments of the source block that are associated with the first logical group. The method further includes consolidating the identified valid memory fragments associated with the first logical group.
    Type: Application
    Filed: January 15, 2019
    Publication date: July 16, 2020
    Applicant: Western Digital Technologies, Inc.
    Inventors: Ramkumar Ramamurthy, Ramanathan Muthiah
  • Patent number: 10635580
    Abstract: Apparatus, systems, methods, and computer program products for buffering storage device data in a host memory buffer (HMB) are presented. A non-volatile memory and a controller are in communication with a non-volatile memory. A controller is configured to receive an input/output (I/O) operation including data. A controller is configured to transmit at least a portion of data to an HMB of a host device separate from a non-volatile memory and a controller for storage until a trigger event occurs.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: April 28, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Kalpit Bordia, Raghavendra Gopalakrishnan, Sachin Krishna Kudva, Ashim Ranjan Saikia, Bhanushankar Doni Gurudath, Ramanathan Muthiah, Pradeep Sreedhar, Prashanth Reddy Enukonda, Ramkumar Ramamurthy
  • Patent number: 10635343
    Abstract: Apparatuses, systems, methods, and computer program products for streamed program commands with periodic garbage collection are disclosed. A controller is configured to set up a data path between the controller and a memory device to initialize an open mode. A controller is configured to perform a plurality of program operations on a memory device in an open mode using a same set up data path. A controller is configured to, in response to exiting an open mode, perform a garbage collection operation on a memory device.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: April 28, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ramanathan Muthiah, Balaji Thraksha Venkataramanan, Ramkumar Ramamurthy, Ravi Gaja