Abstract: A method for operating an analog-to-digital converter (ADC) is provided. The ADC includes a comparator, a sampling switch coupled between a device outputting an analog voltage and an input of the comparator, and a capacitor array including capacitors, wherein top plates of the capacitors are coupled between the sampling switch and the input of the comparator. The method includes, during a first phase, closing the sampling switch and coupling bottom plates of the capacitors to a common mode voltage, during a second phase, decoupling the bottom plates of the capacitors from the common mode voltage while the sampling switch is closed, during a third phase, opening the sampling switch while the bottom plates of the capacitors are decoupled from the common mode voltage, and, during a fourth phase, coupling the bottom plates of capacitors to the common mode voltage while the sampling switch is open.

Abstract: An integrated circuit is provided with a terminal that functions to pass a data signal during a high-speed data mode of operation and to pass an audio signal during an audio mode of operation. The integrated circuit includes an audio source that couples to the terminal through an audio pass transistor during the audio mode of operation. To maintain the audio pass transistor off during the high-speed data mode of operation, the integrated circuit includes a first transistor coupled between the terminal and a gate of the audio pass transistor. The first transistor conducts negative charge from the terminal to the gate of the audio pass transistor.

Abstract: In one implementation, an apparatus, such as an ESD protection circuit, is disclosed. The apparatus can include a filter coupled between a local supply voltage rail to a supply voltage rail. A switch circuit can be connected in parallel with the filter. The apparatus can include a clamp configured to 1) provide a first ESD shunt path from an input line to the local supply voltage rail and 2) provide a second ESD shunt path from the input line to a lower voltage rail. A second clamp can be configured to provide a third ESD shunt path from the local supply voltage rail to the lower voltage rail. The switch circuit can be configured to close a switch to bypass the filter.

Abstract: Described embodiments include a protection circuit having a voltage attenuator circuit with an input coupled to a switch terminal. A filter circuit has a filter input coupled to the output of the attenuator. A first transistor has a first current terminal coupled to a power supply terminal, and a first control terminal coupled to the filter output. A second transistor, which is matched to the first transistor, has a third current terminal coupled to the first current terminal, a second control terminal coupled to the first control terminal, and a fourth current terminal coupled to a first voltage sense terminal. A buffer circuit has a buffer input coupled to the attenuator output. A S/H circuit has a sample input coupled to the buffer output, and a sample output providing a minimum ringing voltage of a signal from the switch terminal.

Abstract: Techniques for valley detection in flyback power converters. In an example, circuitry implementing the techniques is configured to generate a first indication of an over-voltage protection (OVP) condition of a flyback power converter, using a switching terminal signal of the flyback power converter. The circuitry is further configured to generate a second indication of an input voltage surge condition of the flyback power converter, using the switching terminal signal of the flyback power converter. The circuitry further is further configured to suppress the first indication, responsive to the second indication being generated.

Abstract: A speaker impedance measurement includes a test phase and a measurement phase. In the measurement phase, an output amplifier drives a speaker with an output voltage and an output current. A first amplifier amplifies the output voltage to produce a first output signal. A second amplifier amplifies a sense resistor voltage from a sense resistor conducting the output current to produce second output signal. A processor measures the speaker impedance responsive to a function of the first and second output signals, ideal gains of the first and second amplifiers, and an at least one calibration factor. During the test phase, the at least one calibration factor is calculated with respect to a calibration load.

Abstract: An example of an apparatus includes a transimpedance amplifier (TIA) and an integrator circuit that includes an operational amplifier, a capacitor coupled between the operational amplifier's inverting input and output, a first FET coupled between the inverting input of the op amp and the output of the TIA, a resistive element connected to a lower supply rail, and a second FET coupled between the inverting input of the TIA and the resistive element and having a second gate connected to the output of the operational amp.

Abstract: In one implementation, an apparatus, such as an ESD protection circuit, is disclosed. The apparatus can include a filter coupled between a local supply voltage rail to a supply voltage rail. A switch circuit can be connected in parallel with the filter. The apparatus can include a clamp configured to 1) provide a first ESD shunt path from an input line to the local supply voltage rail and 2) provide a second ESD shunt path from the input line to a lower voltage rail. A second clamp can be configured to provide a third ESD shunt path from the local supply voltage rail to the lower voltage rail. The switch circuit can be configured to close a switch to bypass the filter.

Abstract: A transmission line includes an equalization circuit. The equalization circuit is a second-order equalization circuit having a first loop at a gain element and a second loop at the gain element. The first loop may include a first compensation capacitor, and the second loop may include a second compensation capacitor and a resistor. The second order equalization circuit may allow for improved performance with respect to gain as well as reduced power usage.

Abstract: A differential ESD circuit is provided for protecting a pair of differential terminals of an integrated circuit from electrostatic shock. A first diode couples between a first terminal in the pair of differential terminals and a first resistor that couples to a voltage node of the integrated circuit. Similarly, a second diode couples between a second terminal in the pair of differential terminals and a second resistor that couples to the voltage node of the integrated circuit. The first and second resistors isolate the first and second terminals from a capacitive loading that would otherwise exist from the first and second diodes.

Abstract: A voltage comparator includes a boosting circuit that is configured to boost a direct current (DC) bias of the comparator. The boosting circuit includes transistors that are different in size, a larger one of the transistors being configured to add a portion of boosting current to a bias current.

Abstract: A differential ESD circuit is provided for protecting a pair of differential terminals of an integrated circuit from electrostatic shock. A first diode couples between a first terminal in the pair of differential terminals and a first resistor that couples to a voltage node of the integrated circuit. Similarly, a second diode couples between a second terminal in the pair of differential terminals and a second resistor that couples to the voltage node of the integrated circuit. The first and second resistors isolate the first and second terminals from a capacitive loading that would otherwise exist from the first and second diodes.

Abstract: An integrated circuit is provided with a terminal that functions to pass a data signal during a high-speed data mode of operation and to pass an audio signal during an audio mode of operation. The integrated circuit includes an audio source that couples to the terminal through an audio pass transistor during the audio mode of operation. To maintain the audio pass transistor off during the high-speed data mode of operation, the integrated circuit includes a first transistor coupled between the terminal and a gate of the audio pass transistor. The first transistor conducts negative charge from the terminal to the gate of the audio pass transistor.

Abstract: An ESD trigger circuit is provided for protecting a pass transistor coupled to an integrated circuit terminal. The integrated circuit terminal couples through a diode to a voltage node. In response to an electrostatic shock at the integrated circuit terminal, the diode conducts charge to the voltage node to pulse a voltage of the voltage node. The ESD trigger circuit responds to the pulse of the voltage by coupling the voltage node to a gate of the pass transistor.

Abstract: Circuits and methods for suppression of negative transient voltage may be implemented in systems that combine high-speed data, audio, and charging at a plug. The circuits and methods for suppression of the negative transient voltage may include a first diode and transistor coupled in series between a pin and ground, where the transistor is controlled by an output of a voltage comparator that is also coupled to the first pin. A negative transient voltage event may cause the comparator to activate the transistor to sink a current through the diode.

Abstract: A transmission line includes an equalization circuit. The equalization circuit is a second-order equalization circuit having a first loop at a gain element and a second loop at the gain element. The first loop may include a first compensation capacitor, and the second loop may include a second compensation capacitor and a resistor. The second order equalization circuit may allow for improved performance with respect to gain as well as reduced power usage.

Abstract: A voltage comparator includes a boosting circuit that is configured to boost a direct current (DC) bias of the comparator. The boosting circuit includes transistors that are different in size, a larger one of the transistors being configured to add a portion of boosting current to a bias current.

Abstract: Certain aspects of the present disclosure are generally directed to circuitry and techniques for voltage-to-current conversion. For example, certain aspects provide a circuit for signal amplification including a first amplifier; a first transistor, a gate of the first transistor being coupled to an output of the first amplifier and a drain of the first transistor being coupled to an output node of circuit; a first resistive element coupled between a first input node of the circuit and an input of the first amplifier; a second amplifier; a second transistor, a gate of the second transistor being coupled to an output of the second amplifier and a drain of the second transistor being coupled to the output node of circuit; and a second resistive element coupled between a second input node of the circuit and an input of the second amplifier.

Abstract: A method for operating a resonant converter in a burst mode includes determining the polarity of a transformer voltage across a secondary winding of a transformer. The method includes determining, from the polarity of the transformer voltage, on/off states of first and second transistors coupled to the secondary winding of the transformer. If the transformer voltage has a first polarity, the method includes commencing a burst period by alternately turning on/off high-side and low-side transistors electrically connected to a primary winding of the transformer.

Abstract: A trigger circuit includes a first capacitor and a second capacitor connected in series, a control device and an output of the trigger circuit. The first capacitor is connected to a first voltage rail and to a common node. The second capacitor is connected to a second voltage rail and to the common node. The control device has a first terminal that is coupled to the common node and a control terminal to receive a control signal. The control signal may be decoupled from transients on the first voltage rail and the second voltage rail. The output of the trigger circuit is coupled to the common node.