Patents by Inventor Ramnath Bommu Sabbiah SWAMY

Ramnath Bommu Sabbiah SWAMY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit design
    Patent number: 9984194
    Abstract: A computer-implemented method of integrated circuit design comprises: using a computer, producing an integrated circuit layout for multiple instances of a circuitry element, wherein interface components in one instance of said circuitry element communicate with complementary interface components in an adjacent instance of said circuitry element, said interface components being identical between said multiple instances; said producing step comprising: for one instance of said circuitry element, generating an integrated circuit layout for said one instance of said circuitry element on the basis of timing parameters of said complementary interface components with which said one instance communicates in use; detecting timing characteristics of said interface components of said one instance of said circuitry element; applying said detected timing characteristics as said timing parameters of said complementary interface components; and repeating said generating step.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: May 29, 2018
    Assignee: ARM Limited
    Inventors: Ramnath Bommu Sabbiah Swamy, Robert John Harrison
  • INTEGRATED CIRCUIT DESIGN
    Publication number: 20170076033
    Abstract: A computer-implemented method of integrated circuit design comprises: using a computer, producing an integrated circuit layout for multiple instances of a circuitry element, wherein interface components in one instance of said circuitry element communicate with complementary interface components in an adjacent instance of said circuitry element, said interface components being identical between said multiple instances; said producing step comprising: for one instance of said circuitry element, generating an integrated circuit layout for said one instance of said circuitry element on the basis of timing parameters of said complementary interface components with which said one instance communicates in use; detecting timing characteristics of said interface components of said one instance of said circuitry element; applying said detected timing characteristics as said timing parameters of said complementary interface components; and repeating said generating step.
    Type: Application
    Filed: September 15, 2015
    Publication date: March 16, 2017
    Inventors: Ramnath Bommu Sabbiah SWAMY, Robert John HARRISON