Patents by Inventor Ramoji Karumuri Rao

Ramoji Karumuri Rao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated metal layer aware optimization of integrated circuit designs
    Patent number: 10360341
    Abstract: Systems and techniques are described for optimizing an integrated circuit (IC) design. Before routing is performed on the IC design in an IC design flow, an IC design tool can iteratively perform a set of operations, the set of operations comprising: (1) modifying a net in the IC design to obtain a modified net, (2) determining a metal layer for routing the modified net, (3) computing a resistance value and a capacitance value of the modified net based on the metal layer, and (4) computing a delay value for the modified net based on the resistance value and the capacitance value.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: July 23, 2019
    Assignee: Synopsys, Inc.
    Inventors: Abhijeet Chakraborty, David John Seibert, Pingkan Fok, Ramoji Karumuri Rao
  • INTEGRATED METAL LAYER AWARE OPTIMIZATION OF INTEGRATED CIRCUIT DESIGNS
    Publication number: 20190065656
    Abstract: Systems and techniques are described for optimizing an integrated circuit (IC) design. Before routing is performed on the IC design in an IC design flow, an IC design tool can iteratively perform a set of operations, the set of operations comprising: (1) modifying a net in the IC design to obtain a modified net, (2) determining a metal layer for routing the modified net, (3) computing a resistance value and a capacitance value of the modified net based on the metal layer, and (4) computing a delay value for the modified net based on the resistance value and the capacitance value.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 28, 2019
    Applicant: Synopsys, Inc.
    Inventors: Abhijeet Chakraborty, David John Seibert, Pingkan Fok, Ramoji Karumuri Rao
  • Flip-chip integrated circuit routing to I/O devices
    Patent number: 6674166
    Abstract: Tile-based routing between a bump pad and an input/output (I/O) device for implementation on a flip-chip integrated circuit (IC) die. A trace is routed between the bump pad and a position corresponding to a first I/O slot, the first I/O slot being at least partially occupied by the I/O device. A position is obtained for a device pad for the I/O device. The trace is then extended into an area corresponding to the position obtained for the device pad. It is a feature of this aspect of the invention that the trace extension extends the trace into a pad area for a second I/O slot, the second I/O slot being at least partially occupied by the I/O device. The invention also concerns a flip-chip integrated circuit (IC) die that includes a bump pad, an input/output (I/O) device, and a device pad electrically connected to the I/O device and disposed vertically adjacent to a portion of the I/O device.
    Type: Grant
    Filed: January 19, 2001
    Date of Patent: January 6, 2004
    Assignee: LSI Logic Corporation
    Inventors: Ramoji Karumuri Rao, Mike Liang
  • Flip-chip integrated circuit routing to I/O devices
    Publication number: 20010020746
    Abstract: Tile-based routing between a bump pad and an input/output (I/O) device for implementation on a flip-chip integrated circuit (IC) die. A trace is routed between the bump pad and a position corresponding to a first I/O slot, the first I/O slot being at least partially occupied by the I/O device. A position is obtained for a device pad for the I/O device. The trace is then extended into an area corresponding to the position obtained for the device pad. It is a feature of this aspect of the invention that the trace extension extends the trace into a pad area for a second I/O slot, the second I/O slot being at least partially occupied by the I/O device. The invention also concerns a flip-chip integrated circuit (IC) die that includes a bump pad, an input/output (I/O) device, and a device pad electrically connected to the I/O device and disposed vertically adjacent to a portion of the I/O device.
    Type: Application
    Filed: January 19, 2001
    Publication date: September 13, 2001
    Inventors: Ramoji Karumuri Rao, Mike Liang
  • Flip-chip integrated circuit routing to I/O devices
    Patent number: 6225143
    Abstract: Tile-based routing between a bump pad and an input/output (I/O) device for implementation on a flip-chip integrated circuit (IC) die. A trace is routed between the bump pad and a position corresponding to a first I/O slot, the first I/O slot being at least partially occupied by the I/O device. A position is obtained for a device pad for the I/O device. The trace is then extended into an area corresponding to the position obtained for the device pad. It is a feature of this aspect of the invention that the trace extension extends the trace into a pad area for a second I/O slot, the second I/O slot being at least partially occupied by the I/O device. The invention also concerns a flip-chip integrated circuit (IC) die that includes a bump pad, an input/output (I/O) device, and a device pad electrically connected to the I/O device and disposed vertically adjacent to a portion of the I/O device.
    Type: Grant
    Filed: June 3, 1998
    Date of Patent: May 1, 2001
    Assignee: LSI Logic Corporation
    Inventors: Ramoji Karumuri Rao, Mike Liang