Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.

Abstract: A computer-implemented method is provided that is performed in a computer having a processor and multiple co-processors. The method includes launching a same set of operations in each of an original co-processor and a redundant co-processor, from among the multiple co-processors, to obtain respective execution signatures from the original co-processor and the redundant co-processor. The method further includes detecting an error in an execution of the set of operations by the original co-processor, by comparing the respective execution signatures. The method also includes designating the execution of the set of operations by the original co-processor as error-free and committing a result of the execution, responsive to identifying a match between the respective execution signatures.

Abstract: A computer-implemented method is provided that is performed in a computer having a processor and multiple co-processors. The method includes launching a same set of operations in each of an original co-processor and a redundant co-processor, from among the multiple co-processors, to obtain respective execution signatures from the original co-processor and the redundant co-processor. The method further includes detecting an error in an execution of the set of operations by the original co-processor, by comparing the respective execution signatures. The method also includes designating the execution of the set of operations by the original co-processor as error-free and committing a result of the execution, responsive to identifying a match between the respective execution signatures.

Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.

Abstract: A computer-implemented method is provided that is performed in a computer having a processor and multiple co-processors. The method includes launching a same set of operations in each of an original co-processor and a redundant co-processor, from among the multiple co-processors, to obtain respective execution signatures from the original co-processor and the redundant co-processor. The method further includes detecting an error in an execution of the set of operations by the original co-processor, by comparing the respective execution signatures. The method also includes designating the execution of the set of operations by the original co-processor as error-free and committing a result of the execution, responsive to identifying a match between the respective execution signatures.

Abstract: A computer-implemented method is provided that is performed in a computer having a processor and multiple co-processors. The method includes launching a same set of operations in each of an original co-processor and a redundant co-processor, from among the multiple co-processors, to obtain respective execution signatures from the original co-processor and the redundant co-processor. The method further includes detecting an error in an execution of the set of operations by the original co-processor, by comparing the respective execution signatures. The method also includes designating the execution of the set of operations by the original co-processor as error-free and committing a result of the execution, responsive to identifying a match between the respective execution signatures.

Abstract: An aspect includes optimizing an application workflow. The optimizing includes characterizing the application workflow by determining at least one baseline metric related to an operational control knob of an embedded system processor. The application workflow performs a real-time computational task encountered by at least one mobile embedded system of a wirelessly connected cluster of systems supported by a server system. The optimizing of the application workflow further includes performing an optimization operation on the at least one baseline metric of the application workflow while satisfying at least one runtime constraint. An annotated workflow that is the result of performing the optimization operation is output.

Abstract: An aspect includes optimizing an application workflow. The optimizing includes characterizing the application workflow by determining at least one baseline metric related to an operational control knob of an embedded system processor. The application workflow performs a real-time computational task encountered by at least one mobile embedded system of a wirelessly connected cluster of systems supported by a server system. The optimizing of the application workflow further includes performing an optimization operation on the at least one baseline metric of the application workflow while satisfying at least one runtime constraint. An annotated workflow that is the result of performing the optimization operation is output.

Abstract: An aspect includes optimizing an application workflow. The optimizing includes characterizing the application workflow by determining at least one baseline metric related to an operational control knob of an embedded system processor. The application workflow performs a real-time computational task encountered by at least one mobile embedded system of a wirelessly connected cluster of systems supported by a server system. The optimizing of the application workflow further includes performing an optimization operation on the at least one baseline metric of the application workflow while satisfying at least one runtime constraint. An annotated workflow that is the result of performing the optimization operation is output.