Abstract: Multi-phase clocks are used to encode and decode signals that are phase-modulated. The input signal is phase-compared with a feedback clock. Phase differences increment or decrement an up/down counter. The count value from the up/down counter is applied to a phase rotator, which selects one clock phase from a bank of multi-phase clocks. The multi-phase clocks have the same frequency, but are offset in phase from each other. An output divider divides the selected multi-phase clock to generate a phase-modulated output. A feedback divider divides a fixed-phase clock from the multi-phase clocks to generate the feedback clock. An analog or a digital front-end may be used to convert analog inputs to digital signals to increment or decrement the counter, or to encode multiple digital bits as phase assignments. For a de-modulator, a digital-to-analog converter (DAC) or a digital decoder produces the final output from the count of the up/down counter.

Abstract: A loop-back extender card is plugged into a memory module socket on a personal computer (PC) motherboard. The extender card has a test socket that receives a memory module under test. An Advanced Memory Buffer (AMB) on the memory module fully buffers DRAM chips on the memory module. The AMB inputs from and outputs to the test socket differential northbound lanes (toward a processor) and southbound lanes (away from the processor). The extender card has northbound loopback traces that connect northbound lane outputs from the memory module back to northbound-lane inputs to the memory module. Southbound loopback traces connect southbound lane outputs from the memory module back to southbound-lane inputs to the memory module. The loop-back extender card allows the AMB to perform loopback testing without modifying the PC motherboard. Series/shunt resistors can be placed on the loopback traces, or serpentine traces can be used to increase loopback delays.

Abstract: Two heat chambers are placed side-by-side. Heated air is blown upward through a first chamber and downward through a second heat chamber. An upper heating unit has a blower and heater that heat air exiting the first chamber and blows the heated air into the top of the second chamber. A lower heating unit has a blower and heater that heat air exiting the second chamber and blows the heated air into the top of the first chamber. Air is circulated in a loop through the two heat chambers by the two heating units. Inefficiencies from return pipes are eliminated by using the second chamber. The heated air is blown past memory modules under test in a heat chamber that has an insulated backplane. Pattern-generator cards outside the heat chamber exercise the memory modules and are cooled while memory modules in the heat chamber are heated.

Abstract: Memory modules with an extra dynamic-random-access memory (DRAM) chip for storing error-correction code (ECC) are tested on a personal computer (PC) motherboard tester using a cross-over extender card inserted into a memory module socket on the motherboard. ECC code generated on the motherboard is normally stored in the extra ECC DRAM chip, preventing test patterns such as checkerboards and walking-ones to be written directly to the ECC DRAM chip. During testing, the cross-over extender card routes signals from the motherboard for one of the data DRAM chips to the ECC DRAM chip, while the ECC code is routed to one of the data DRAM chips. The checkerboard or other test pattern is thus written and read from the ECC DRAM chip that normally stores the ECC code. The cross-over extender card can be hardwired, or can have a switch to allow normal operation or testing of the ECC DRAM chip.

Abstract: Hot air blown past memory modules under test in a heat chamber is improved. Hot air entering the chamber from an inlet pipe is split by a manifold and deflectors. Holes in the manifold allow for a relatively even air distribution within the chamber, minimizing temperature variations. Return air is collected by a heat-chamber bottom cover into a return pipe. A heating unit re-heats the return air and blows it into the inlet pipe. One side of the heat chamber is an insulated backplane. Memory modules are inserted into sockets on module motherboards, which are inserted into motherboard sockets on the backplane. On the other side of the backplane, card sockets receive pattern-generator cards outside the heat chamber but electrically connected to the module motherboards through the backplane. The pattern-generator cards exercise the memory modules. The pattern-generator cards are cooled while memory modules in the heat chamber are heated.

Abstract: A phase-locked loop wherein the output signal is effectively sampled at an increased rate from conventional phase-locked loops, allowing for a greater increase in the ratio of the output frequency to the input frequency while reducing the possibility of jitter or failure to lock. Multiple differently phased reference signals and correspondingly phased feedback signals are produced. The comparison of the feedback signals and the reference signals produce multiple error signals which are combined to adjust the oscillation frequency of the voltage-controlled oscillator.

Abstract: An integrated circuit electrostatic discharge (ESD) protection circuit employs a capacitor and a zener diode to trigger a thick oxide ESD shunt field effect transistor (FET). When an ESD induced voltage at an input or output node reaches the turn-on voltage determined by the zener diode breakdown voltage, the shunting transistor is turned on by current capacitively coupled to the base of the parasitic bipolar transistor inherently formed in the thick oxide FET. The parasitic bipolar transistor is turned on in its saturated mode, substantially shorting the node to ground. At the end of the ESD event when the ESD induced current is no longer sufficient to keep the shunting transistor in its saturated mode, the shunting transistor turns off and the ESD protection circuit returns to its off mode, monitoring the input or output node for the occurrence of another ESD event.

Abstract: A field effect transistor device formed on an integrated circuit chip substrate and driven by the on-chip voltages having a well region formed in the substrate, and source and drain regions one of which is formed in the well region. The well region has a lower doping concentration than the source and drain regions and is of the same conductivity type. The well region provides a reduced electric field gradient at the source/substrate or drain/substrate junction and significantly increases the breakdown resistance of the device to DC voltages higher than the on-chip voltages. An input/output protection circuit employing the field effect transistor coupled in series between an integrated circuit output pad and the active devices on the chip providing ability to withstand coupling of the pad to a relatively high DC voltages.