Abstract: A method, a system and a computer program product suitable for use in a manufacturing environment comprising a multiplicity of nominally identical independent tools. A computing device generates a multi dimensional array of process trace data derived from at least one of the independent tools, wherein, the array includes data representing a first dimension comprising a list of steps in a manufacturing recipe and data representing a second dimension comprising a list of a set of sensors generating measurements from at least one of the independent tools. The computing device conducts an analysis on at least one preselected subset of the multi dimensional array for the purpose of evaluating at least one operating characteristic of at least one of the independent tools. The computing device presents results of the analysis via a set of hierarchically linked and browseable graphics.

Abstract: A method is disclosed which includes patterning a photoresist layer on a substrate of a structure, removing a first portion of the photoresist layer to expose a first area of the substrate, etching the first area to form a cavity having a first depth, removing a second portion of the photoresist to expose an additional area of the substrate, and etching the cavity to expose a first conductor in the structure and the additional area to expose a second conductor in the structure.

Abstract: A method, a system and a computer program product suitable for use in a manufacturing environment comprising a multiplicity of nominally identical independent tools. A computing device generates a multi dimensional array of process trace data derived from at least one of the independent tools, wherein, the array includes data representing a first dimension comprising a list of steps in a manufacturing recipe and data representing a second dimension comprising a list of a set of sensors generating measurements from at least one of the independent tools. The computing device conducts an analysis on at least one preselected subset of the multi dimensional array for the purpose of evaluating at least one operating characteristic of at least one of the independent tools. The computing device presents results of the analysis via a set of hierarchically linked and browseable graphics.

Abstract: A method and system for evaluating a performance of a semiconductor manufacturing tool while manufacturing microelectronic devices are disclosed. At least one report is generated based on executions of at least one statistical test. The report includes at least one heat map having rows that correspond to sensors, columns that correspond to trace data obtained during recipe steps, and cells at the intersection of the rows and the columns. At least one sensor in the tool obtains trace data of a recipe step while manufacturing at least one microelectronic device. A computing device analyzes the obtained trace data to determine a level of operational significance found in the data and assigns a score to the trace data that indicates a level of operational significance. Then, the computing device places the score in a corresponding cell of the heat map. A user uses the cell for evaluating the tool performance.

Abstract: A method is disclosed which includes patterning a photoresist layer on a substrate of a structure, removing a first portion of the photoresist layer to expose a first area of the substrate, etching the first area to form a cavity having a first depth, removing a second portion of the photoresist to expose an additional area of the substrate, and etching the cavity to expose a first conductor in the structure and the additional area to expose a second conductor in the structure.

Abstract: A metal interconnect and an IC chip including the metal interconnect are disclosed. One embodiment of the method may include providing an integrated circuit (IC) chip up to and including a middle of line (MOL) layer, the MOL layer including a contact positioned within a first dielectric; recessing the first dielectric such that the contact extends beyond an upper surface of the first dielectric; forming a second dielectric over the first dielectric such that the second dielectric surrounds at least a portion of the contact, the second dielectric having a lower dielectric constant than the first dielectric; forming a planarizing layer over the second dielectric; forming an opening through the planarizing layer and into the second dielectric to the contact; and forming a metal in the opening to form the metal interconnect.

Abstract: A method and system for evaluating a performance of a semiconductor manufacturing tool while manufacturing microelectronic devices are disclosed. At least one report is generated based on executions of at least one statistical test. The report includes at least one heat map having rows that correspond to sensors, columns that correspond to trace data obtained during recipe steps, and cells at the intersection of the rows and the columns. At least one sensor in the tool obtains trace data of a recipe step while manufacturing at least one microelectronic device. A computing device analyzes the obtained trace data to determine a level of operational significance found in the data and assigns a score to the trace data that indicates a level of operational significance. Then, the computing device places the score in a corresponding cell of the heat map. A user uses the cell for evaluating the tool performance.

Abstract: A metal interconnect and an IC chip including the metal interconnect are disclosed. One embodiment of the method may include providing an integrated circuit (IC) chip up to and including a middle of line (MOL) layer, the MOL layer including a contact positioned within a first dielectric; recessing the first dielectric such that the contact extends beyond an upper surface of the first dielectric; forming a second dielectric over the first dielectric such that the second dielectric surrounds at least a portion of the contact, the second dielectric having a lower dielectric constant than the first dielectric; forming a planarizing layer over the second dielectric; forming an opening through the planarizing layer and into the second dielectric to the contact; and forming a metal in the opening to form the metal interconnect.

Abstract: Methods of forming a metal interconnect and an IC chip including the metal interconnect are disclosed. One embodiment of the method may include providing an integrated circuit (IC) chip up to and including a middle of line (MOL) layer, the MOL layer including a contact positioned within a first dielectric; recessing the first dielectric such that the contact extends beyond an upper surface of the first dielectric; forming a second dielectric over the first dielectric such that the second dielectric surrounds at least a portion of the contact, the second dielectric having a lower dielectric constant than the first dielectric; forming a planarizing layer over the second dielectric; forming an opening through the planarizing layer and into the second dielectric to the contact; and forming a metal in the opening to form the metal interconnect.

Abstract: An interconnect structure having an incomplete via opening is processed to deepen a via opening and to expose a metal line. In case the interconnect structure comprises a metal pad or a blanket metal layer, the metal pad or the metal layer is removed selective to an underlying dielectric layer to expose the incomplete via opening. Another dielectric layer is formed within the incomplete via opening to compensated for differences in the total dielectric thickness above the metal line relative to an optimal dielectric stack. A photoresist is applied thereupon and patterned. An anisotropic etch process for formation of a normal via opening may be employed with no or minimal modification to form a proper via opening and to expose the metal line. A metal pad is formed upon the metal line so that electrical contact is provided between the metal pad and the metal line.

Abstract: Methods of forming a metal interconnect and an IC chip including the metal interconnect are disclosed. One embodiment of the method may include providing an integrated circuit (IC) chip up to and including a middle of line (MOL) layer, the MOL layer including a contact positioned within a first dielectric; recessing the first dielectric such that the contact extends beyond an upper surface of the first dielectric; forming a second dielectric over the first dielectric such that the second dielectric surrounds at least a portion of the contact, the second dielectric having a lower dielectric constant than the first dielectric; forming a planarizing layer over the second dielectric; forming an opening through the planarizing layer and into the second dielectric to the contact; and forming a metal in the opening to form the metal interconnect.