Abstract: The invention relates to a semiconductor wafer (1) having a plurality of first sawing regions (201-211) running parallel to one another in a first direction (X) and a plurality of second sawing regions (301-311) running parallel to one another in a second direction (Y), having useful regions (10) which in each case contain an integrated circuit (100) and which are in each case arranged between respective adjacent first sawing regions (201-211) and respective adjacent second sawing regions (301-311), and at least one test structure region arranged in the first sawing regions (201-211) and the second sawing regions (301-311) with test structures formed therein for checking electrical parameters of semiconductor elements.

Abstract: A semiconductor disk which exhibits chip areas arranged next to one another and separated from one another by a kerf. The chip areas in each case exhibit a multiplicity of similar device patterns, such that at least one fill area with fill patterns is arranged in the kerf, and the fill patterns in the kerf and the device patterns in the chip areas are essentially similarly constructed.

Abstract: The invention relates to a semiconductor wafer (1) having a plurality of first sawing regions (201-211) running parallel to one another in a first direction (X) and a plurality of second sawing regions (301-311) running parallel to one another in a second direction (Y), having useful regions (10) which in each case contain an integrated circuit (100) and which are in each case arranged between respective adjacent first sawing regions (201-211) and respective adjacent second sawing regions (301-311), and at least one test structure region arranged in the first sawing regions (201-211) and the second sawing regions (301-311) with test structures formed therein for checking electrical parameters of semiconductor elements.

Abstract: The invention proposes a semiconductor wafer with a test structure for detecting parasitic contact structures on the semiconductor wafer, in which a first interconnect plane (A) contains interconnects (1) running parallel to one another and a second interconnect (2) that is arranged between the latter. The two first interconnects (1) are connected by means of contact elements (4) arranged above them, to a third interconnect (3) that runs in a second interconnect plane (B) transverse to the first and second interconnects, and that also crosses the second interconnect (2). If there is a parasitic contact structure (5) formed between the contact elements (4), which has arisen during the lithographic exposure for producing the contact elements (4) on account of constructively interfering diffraction maxima, then this shorts the second interconnect (2) to the third interconnect (3).