Patents by Inventor Ramprasad Nagaraja Rao

Ramprasad Nagaraja Rao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8909860
    Abstract: Techniques are described for increasing data access performance for a memory device. In various embodiments, a scheduler/controller is configured to manage data as it read to or written from a memory. Read or write access is increased by partitioning a memory into a group of sub-blocks, associating a parity block with the sub-blocks, and accessing the sub-blocks to read data as needed. Write access is increased by including a latency cache that stores data associated with a read command. Once a read-modify write command is received, the data stored in the data cache is used to update the parity block. In a memory without a parity block, write access is increased by adding one or more spare memory blocks to provide additional memory locations for performing write operations to the same memory block in parallel.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: December 9, 2014
    Assignee: Cisco Technology, Inc.
    Inventor: Ramprasad Nagaraja Rao
  • Publication number: 20140059301
    Abstract: Techniques are described for increasing data access performance for a memory device. In various embodiments, a scheduler/controller is configured to manage data as it read to or written from a memory. Read or write access is increased by partitioning a memory into a group of sub-blocks, associating a parity block with the sub-blocks, and accessing the sub-blocks to read data as needed. Write access is increased by including a latency cache that stores data associated with a read command. Once a read-modify write command is received, the data stored in the data cache is used to update the parity block. In a memory without a parity block, write access is increased by adding one or more spare memory blocks to provide additional memory locations for performing write operations to the same memory block in parallel.
    Type: Application
    Filed: August 23, 2012
    Publication date: February 27, 2014
    Applicant: Cisco Technology, Inc.
    Inventor: Ramprasad Nagaraja RAO
  • Patent number: 8467294
    Abstract: In one embodiment, a method includes receiving a packet at an input port of a network device, the input port having a plurality of queues with at least one queue for each output port at the network device, identifying a port group for transmitting the packet from the network device, the port group having a plurality of members each associated with one of the output ports, and selecting one of the queues based on utilization of the members. An apparatus for load balancing is also disclosed.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: June 18, 2013
    Assignee: Cisco Technology, Inc.
    Inventors: Pirabhu Raman, Deepak Cherian, Hariharan Balasubramanian, Ramprasad Nagaraja Rao
  • Publication number: 20120207175
    Abstract: In one embodiment, a method includes receiving a packet at an input port of a network device, the input port having a plurality of queues with at least one queue for each output port at the network device, identifying a port group for transmitting the packet from the network device, the port group having a plurality of members each associated with one of the output ports, and selecting one of the queues based on utilization of the members. An apparatus for load balancing is also disclosed.
    Type: Application
    Filed: February 11, 2011
    Publication date: August 16, 2012
    Applicant: CISCO TECHNOLOGY, INC.
    Inventors: Pirabhu Raman, Deepak Cherian, Hariharan Balasubramanian, Ramprasad Nagaraja Rao