Abstract: A communications cabling front-end architecture that achieves solid echo cancellation and lower noise performance by combining an echo-cancellation circuit and an equalizer function at the same point, at the most front-end of the system.

Abstract: A driver for a vertical-cavity surface emitting laser (VCSEL) is provided that includes a bias current source, a modulation current source, and an output tracking circuit. The bias current source is operable to generate a bias current and an output voltage for the VCSEL and to generate a replica output voltage. The modulation current source is coupled to the bias current source by at least one switch and is operable to generate a modulation current for the VCSEL when the switch is closed. The output tracking circuit is coupled to the bias current source. The output tracking circuit is operable to generate a feedback signal for the bias current source based on the output voltage and the replica output voltage. The bias current source is also operable to generate the output voltage and the replica output voltage based on the feedback signal.

Abstract: A circuit and method for comparing and providing a signal indicative of a difference in magnitude between a differential signal voltage and a differential reference voltage.

Abstract: A driver for a vertical-cavity surface emitting laser (VCSEL) is provided that includes a bias current source, a modulation source, and a peaking control circuit. The bias current source is operable to generate a bias current for the VCSEL and an output voltage. The modulation current source is coupled to the bias current source by at least one switch and is operable to generate a modulation current for the VCSEL when the switch is closed. The peaking control circuit is coupled to the bias current source. The peaking control circuit is operable to receive the output voltage from the bias current source and to generate a driver output voltage for the VCSEL based on the output voltage. The driver output voltage has less peaking than the output voltage.

Abstract: A system and a method are disclosed for providing a constant swing high-gain complementary differential limiting amplifier. High gain for the differential amplifier is created by providing a current to the driving transistors that is a combination of any of (a) constant current, (b) transconductance based current, and (c) temperature compensated based current. A constant differential output swing is created by providing a varying differential current to the output load resistors of the differential amplifier that tracks process and temperature variations within the output load resistors.

Abstract: An input network is provided within an integrated circuit for interfacing with signals produced by an external CML driver apparatus. The input network includes an input for receiving the signals, and this input is coupled to a terminating impedance, a DC attenuator and an AC attenuator. A common-mode correction loop is coupled to the AC attenuator and the DC attenuator for rejecting common-mode noise generated by the CML driver apparatus. The common-mode correction loop can also provide a common-mode voltage suitable for facilitating high-speed operation of low-voltage devices in the internal data path of the integrated circuit. An amplifier can be provided to compensate for signal attenuation in the input network.

Abstract: A circuit and method are provided for performing built-in test of output signal magnitudes of integrated differential signal generator circuitry. In accordance with one embodiment, first upper and lower reference voltages and second upper and lower reference voltages are received via a plurality of reference electrodes, wherein: a difference between the first and upper and lower reference voltages comprises a first difference magnitude; a difference between the second upper and lower reference voltages comprises a second difference magnitude; and the first difference magnitude is greater than the second difference magnitude. Test signal generator circuitry provides a plurality of binary signals with respective successions of opposing signal states.

Abstract: Integrated differential data signal generator circuitry for providing differential data signals with controlled rise and fall times and built-in test capabilities.

Abstract: A digital-to-analog converter is provided that includes an input stage and an output stage. The input stage is operable to receive a digital bit of data, to convert the digital bit into a quasi-differential current, and to convert the quasi-differential current into a first voltage using a load that is comprised of transconductance and resistance. The output stage is coupled to the input stage and is operable to generate analog data based on the first voltage.

Abstract: A circuit with low noise and reduced offset that feeds an input of an opamp with a programmable feedback resistor that provides variable gain settings. Input biasing currents are varied using control bits that are also used to adjust the gain. When the input signal is small (gain at higher setting), a minimum bias current is provided to source the input voltage swing. This scheme reduces the noise and offset generated by the lower transconductance of a biasing transistor while maintaining a constant SNR and fixed offset even in the presence of relatively small input swings. Also, when the input signal is large (gain at lower setting), a maximum bias current can be provided to accommodate the relatively large input swing level. Although the overall noise and offset current are increased for large input swings, the overall SNR and offset is maintained for relatively lower input swings.

Abstract: There is disclosed high-speed current-mirror circuitry and methods of operating the same. An exemplary impedance-peaking current mirror comprises a N-channel drive transistor and a N-channel mirror transistor. The N-channel drive transistor has a source coupled to ground, a drain coupled to a current source and a gate coupled to the drain via a series connection of a resistor and an inductor. The N-channel mirror transistor has a source coupled to ground, a gate coupled to the drain of the N-channel drive transistor, and a drain coupled to a positive power supply via an impedance load.

Abstract: A low power analog equalizer is disclosed that provides up to twenty decibels (20 dB) of alternating current gain in a single stage of analog signal equalization. The analog equalizer comprises an operational amplifier coupled to two half circuits. Each half circuit comprises an impedance network capable of receiving an analog input voltage and generating a current signal that is inversely proportional to frequency, a current steering digital to analog converter capable of adjusting the gain of the operational amplifier, and a transistor and an amplifier coupled in a cascode configuration to create a low impedance node at the output of the impedance network. The analog equalizer is fabricated with 0.18 micron CMOS technology and operates at 1.8 volts.