Abstract: Techniques are provided to form semiconductor devices that include one or more gate cuts having a layer of polymer material at edges of the gate cut. The polymer layer may be provided as a byproduct of the etching process used to form the gate cut recess through the gate structure, and can protect any exposed portions of the source or drain regions from certain subsequent processes. The gate structure may be interrupted between two transistors with a gate cut that extends through an entire thickness of the gate structure and includes a dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. The edges of the gate cut may be lined with a polymer layer that is also on any exposed portions of the source or drain regions that were exposed during the etching process used to form the gate cut recess.

Abstract: Disclosed herein are techniques for fabricating nanoribbon transistors of integrated circuit (IC) structures using early nanoribbon release with flowable oxide fill, and related methods and devices. The fabrication method disclosed herein is based on performing a nanoribbon release prior Pto forming source/drain (S/D) regions of transistors. Using a flowable oxide fill material may be particularly advantageous in enabling the early nanoribbon release method. In one aspect, an IC structure fabricated using early nanoribbon release with flowable oxide fill may include a base, a subfin portion extending away from the base, and a transistor comprising a stack of nanoribbons above the subfun portion, wherein an upper surface of the base includes a recess proximate to the subfin portion.

Abstract: Techniques are provided herein to form semiconductor devices that include one or more gate cuts having a very high aspect ratio (e.g., an aspect ratio of 5:1 or greater, such as 10:1). In an example, a semiconductor device includes a conductive material that is part of a transistor gate structure around or otherwise on a semiconductor region. The semiconductor region can be, for example, a fin of semiconductor material that extends between a source region and a drain region, or one or more nanowires or nanoribbons of semiconductor material that extend between a source region and a drain region. The gate structure may be interrupted between two transistors with a gate cut that extends through an entire thickness of the gate structure. A particular plasma etching process may be performed to form the gate cut with a very high height-to-width aspect ratio so as to enable densely integrated devices.

Abstract: Techniques are provided to form semiconductor devices that include forksheet transistors with a self-aligned dielectric spine and nanosheets with a wrapped-around gate dielectric. The dielectric spine may be formed prior to the formation of gate structures. In an example, first and second semiconductor devices have first and second semiconductor regions, respectively, extending in a first direction. The first and second semiconductor regions may include any number of nanosheets. A dielectric spine extends in the first direction centrally aligned between the first and second semiconductor regions. The gate dielectric of the gate structures on either side of the dielectric spine is wrapped around the semiconductor regions, such that the gate dielectric is present between the nanosheets and the dielectric spine along the second direction.

Abstract: Techniques are provided to form semiconductor devices with different inner spacer widths and different nanoribbon (e.g., or nanowire, or nanosheet) thickness. In an example, any number of first semiconductor devices include first gate structures around first semiconductor regions and any number of second semiconductor devices include second gate structures around second semiconductor regions. First dielectric inner spacers are provided between the first gate structure and the corresponding source or drain regions of the first semiconductor devices with a first width and second dielectric inner spacers are provided between the second gate structure and the corresponding source or drain regions of the second semiconductor devices with a second width that is greater than the first width. In some such examples, the first semiconductor regions may be thinner compared to the second semiconductor regions to cause a corresponding increase in the threshold voltage of the first semiconductor devices.

Abstract: One or more transistors may have gate structures with differing sidewall slopes. The gate structures may be over stacks of channel regions in nanosheets (or nanoribbons or nanowires), and the differing gate profiles may correspond to differing electrical characteristics. Transistors with metal gate structures may be tuned by strategically etching the gate structures, for example, using lower etch powers, higher etch temperatures, and/or longer etch durations, to achieve substantially vertical gate profiles.

Abstract: Techniques are provided to form semiconductor devices that include one or more gate cuts having a layer of polymer material at edges of the gate cut. The polymer layer may be provided as a byproduct of the etching process used to form the gate cut recess through the gate structure, and can protect any exposed portions of the source or drain regions from certain subsequent processes. The gate structure may be interrupted between two transistors with a gate cut that extends through an entire thickness of the gate structure and includes a dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. The edges of the gate cut may be lined with a polymer layer that is also on any exposed portions of the source or drain regions that were exposed during the etching process used to form the gate cut recess.

Abstract: Techniques are described to form semiconductor devices that include one or more gate cuts having a very high aspect ratio (e.g., an aspect ratio of 5:1 or greater). A semiconductor device includes a conductive material that is part of a transistor gate structure around or otherwise on a semiconductor region. The gate structure may be interrupted between two transistors with a gate cut that extends through an entire thickness of the gate structure. A plasma etching process may be performed to form the gate cut with a very high height-to-width aspect ratio with little to no tapering in its sidewall profile, so as to enable densely integrated devices. Furthermore, an etching process may be performed on a gate masking structure used to pattern the location of the gate cuts to ensure that the gate masking structure has low sidewall taper and sufficiently opened enough to expose the underlying gate.

Abstract: Techniques are provided herein to form semiconductor devices that include one or more gate cuts having a very high aspect ratio (e.g., an aspect ratio of 5:1 or greater, such as 10:1). In an example, a semiconductor device includes a conductive material that is part of a transistor gate structure around or otherwise on a semiconductor region. The semiconductor region can be, for example, a fin of semiconductor material that extends between a source region and a drain region, or one or more nanowires or nanoribbons of semiconductor material that extend between a source region and a drain region. The gate structure may be interrupted between two transistors with a gate cut that extends through an entire thickness of the gate structure. A particular plasma etching process may be performed to form the gate cut with a very high height-to-width aspect ratio so as to enable densely integrated devices.