Abstract: A mass storage device comprising at least one array of memory cells, at least one data path unit in communication with the at least one array, the at least one data path unit comprising a master buffer, and a main data bus adapted to transfer data between the at least one data path unit and an input/output (I/O) unit via a buffer interface unit (BIF) comprising a plurality of slave buffers, the main data bus being further adapted to support at least one of a download and upload of data between the main data bus and the I/O unit, during simultaneous performance of an internal operation between the main data bus and the at least one array, the internal operation comprising at least one of a read, program and erase operation. Methods for operating the mass storage device are also disclosed.

Abstract: Apparatus including a virtual ground array, which includes memory cells connected in rows and columns to word lines and bit lines, respectively. The virtual ground array includes at least one block of data, and peripheral circuitry adapted to simultaneously access a plurality of subsets of the at least one block of data stored in the memory cells along at least one word line. Methods for operating the virtual ground array in a mass storage device include simultaneously accessing a plurality of subsets of at least one block of data stored in the memory cells along at least one word line.

Abstract: A method for operating a memory device, the method comprising marking a portion of a memory device associated with a group of bits comprising at least one bit upon which an operation is to be performed, and operating on the group of bits and skipping operating on at least one unmarked portion of the memory device in an operation cycle of the memory device. A random access memory (RAM) device is also disclosed comprising a plurality of addresses for storing therein data, and at least one address pointer for at least one of the addresses in the RAM device.

Abstract: A flash memory card including a controller, at least one control pad, at least one memory, and a high voltage switch logic module in communication with the at least one control pad, the controller and the at least one memory, the high voltage switch logic module being adapted to selectively route voltage from the at least one control pad to one of the controller and the at least one memory. If the voltage input to the at least one control pad does not exceed a predefined level, then the voltage may be routed from the at least one control pad to the controller. If the voltage input to the at least one control pad exceeds the predefined level, then the voltage may be routed from the at least one control pad to the at least one memory.

Abstract: A method for defect detection, comprising providing a memory cell array comprising memory cells connected to word lines and local bit lines, and global bit lines connected to the local bit lines, the global bit lines comprising at least two portions, one portion connected to a voltage source, and the other portion connected to a defect detector, the defect detector comprising logic circuit components for outputting a logic signal, and detecting a defect comprising at least one of a short circuit and an open circuit in at least one of the word lines, local bit lines and global bit lines by detecting a signal at the defect detector. Embodiments of apparatus for carrying out the methods of the invention are also disclosed.

Abstract: A method for defect detection, comprising providing a memory cell array comprising memory cells connected to word lines and local bit lines, and global bit lines connected to the local bit lines, the global bit lines comprising at least two portions, one portion connected to a voltage source, and the other portion connected to a defect detector, the defect detector comprising logic circuit components for outputting a logic signal, and detecting a defect comprising at least one of a short circuit and an open circuit in at least one of the word lines, local bit lines and global bit lines by detecting a signal at the defect detector. Embodiments of apparatus for carrying out the methods of the invention are also disclosed.

Abstract: A flash memory card including a controller, at least one control pad, at least one memory, and a high voltage switch logic module in communication with the at least one control pad, the controller and the at least one memory, the high voltage switch logic module being adapted to selectively route voltage from the at least one control pad to one of the controller and the at least one memory. If the voltage input to the at least one control pad does not exceed a predefined level, then the voltage may be routed from the at least one control pad to the controller. If the voltage input to the at least one control pad exceeds the predefined level, then the voltage may be routed from the at least one control pad to the at least one memory.

Abstract: A method for operating a memory device, the method comprising marking a portion of a memory device associated with a group of bits comprising at least one bit upon which an operation is to be performed, and operating on the group of bits and skipping operating on at least one unmarked portion of the memory device in an operation cycle of the memory device. A random access memory (RAM) device is also disclosed comprising a plurality of addresses for storing therein data, and at least one address pointer for at least one of the addresses in the RAM device.

Abstract: Apparatus including a virtual ground array, mass storage non-volatile memory device, which includes memory cells connected in rows and columns to word lines and bit lines, respectively. Methods for operating the mass storage device are also disclosed herein.

Abstract: A mass storage device comprising at least one array of memory cells, at least one data path unit in communication with the at least one array, the at least one data path unit comprising a master buffer, and a main data bus adapted to transfer data between the at least one data path unit and an input/output (I/O) unit via a buffer interface unit (BIF) comprising a plurality of slave buffers, the main data bus being further adapted to support at least one of a download and upload of data between the main data bus and the I/O unit, during simultaneous performance of an internal operation between the main data bus and the at least one array, the internal operation comprising at least one of a read, program and erase operation. Methods for operating the mass storage device are also disclosed.

Abstract: The present invention is a device and method for a semiconductor array which attempts to ensure that, during power up, a reference cell becomes valid after one or more data cells. The array includes at least one data cell, at least one cell common line to which the data cell is connected, at least one reference cell, a reference common line to which the references cell is connected and a voltage differentiator. The voltage differentiator is connected to the cell and reference common lines and receives a powering-up power supply voltage from a power supply. The voltage differentiator provides a reference voltage to the reference common line and a cell voltage to the at least one cell common line, wherein the reference voltage is lower than the cell voltage by a predetermined voltage gap.

Abstract: A column of read-only-memory (ROM) cells is programmed to store two or more bits of information in each cell by forming a plurality of coding (bit) lines adjacent to the column of cells, and selectively connecting the cells to the plurality of coding lines so that the different logic conditions defined by the two or more bits are represented by the coding lines that are connected to a memory cell.