Abstract: A network device includes a bus interface and one or more circuits. The bus interface communicates with a memory using a first bus domain, and with user applications using a second bus domain. The one or more circuits execute a first bus function that accesses a region of the memory using a memory-domain MKEY in the first bus domain, execute a second bus function that communicates with the user applications using the second bus domain, and communicates packets over the network for the user applications, wherein processing of the packets includes accessing the region of the memory via a cross-bus-domain MKEY that points to the memory-domain MKEY in the first bus function, and, in response to authorizing access to a sub-region in the region of the memory, defines for the sub-region a cross-security-domain MKEY pointing to the cross-bus-domain MKEY, which in turn points to the memory-domain MKEY.

Abstract: A network device includes a bus interface and one or more circuits. The bus interface communicates with a memory using a first bus domain, and with user applications using a second bus domain. The one or more circuits execute a first bus function that accesses a region of the memory using a memory-domain MKEY in the first bus domain, execute a second bus function that communicates with the user applications using the second bus domain, and communicates packets over the network for the user applications, wherein processing of the packets includes accessing the region of the memory via a cross-bus-domain MKEY that points to the memory-domain MKEY in the first bus function, and, in response to authorizing access to a sub-region in the region of the memory, defines for the sub-region a cross-security-domain MKEY pointing to the cross-bus-domain MKEY, which in turn points to the memory-domain MKEY.

Abstract: A system includes one or more processors, one or more network devices, and a controller device. The network devices are to exchange communication traffic over a network for the one or more processors, by executing work requests issued by the one or more processors. The controller device is to receive the work requests from the one or more processors and distribute the work requests among the network devices.

Abstract: A method for data transfer includes transmitting a sequence of data packets from a first computer over a network to a second computer in a single RDMA data transfer transaction. Upon receipt of a second packet in the sequence without previously having received the first packet, the second computer sends a NAK packet over the network to the first computer, indicating that the first packet was not received. A retransmission mode is selected responsively to the type of the transaction, such that when the transaction is of a first type, the first packet is retransmitted from the first computer to the second computer in response to the NAK packet without retransmitting the second packet, and when the transaction is of a second type, both the first and second packets are retransmitted from the first computer to the second computer in response to the NAK packet.

Abstract: An apparatus includes operational circuitry and Hardware Diagnostics Circuitry (HDC). The HDC is configured to receive a definition of multiple trigger rules, each trigger rule specifying a respective trigger event as a function of trigger data sources in the operational circuitry, to receive a definition of (i) a pre-trigger logging set selected from among a plurality of diagnostics data sources in the operational circuitry, and (ii) for each trigger rule, a respective post-trigger logging set including a set of one or more of the diagnostics data sources, and, during operation of the operational circuitry, to log the diagnostics data sources in the pre-trigger logging set, to log the trigger data sources and to repeatedly evaluate the trigger rules, and, in response to triggering of a given trigger event by a given trigger rule, to start logging the diagnostics data sources in the post-trigger logging set of the given trigger rule.

Abstract: An apparatus includes operational circuitry and Hardware Diagnostics Circuitry (HDC). The HDC is configured to receive a definition of multiple trigger rules, each trigger rule specifying a respective trigger event as a function of trigger data sources in the operational circuitry, to receive a definition of (i) a pre-trigger logging set selected from among a plurality of diagnostics data sources in the operational circuitry, and (ii) for each trigger rule, a respective post-trigger logging set including a set of one or more of the diagnostics data sources, and, during operation of the operational circuitry, to log the diagnostics data sources in the pre-trigger logging set, to log the trigger data sources and to repeatedly evaluate the trigger rules, and, in response to triggering of a given trigger event by a given trigger rule, to start logging the diagnostics data sources in the post-trigger logging set of the given trigger rule.

Abstract: An apparatus includes operational circuitry and Hardware Diagnostics Circuitry (HDC). The HDC is configured to receive a definition of multiple trigger rules, each trigger rule specifying a respective trigger event as a function of trigger data sources in the operational circuitry, to receive a definition of (i) a pre-trigger logging set selected from among a plurality of diagnostics data sources in the operational circuitry, and (ii) for each trigger rule, a respective post-trigger logging set including a set of one or more of the diagnostics data sources, and, during operation of the operational circuitry, to log the diagnostics data sources in the pre-trigger logging set, to log the trigger data sources and to repeatedly evaluate the trigger rules, and, in response to triggering of a given trigger event by a given trigger rule, to start logging the diagnostics data sources in the post-trigger logging set of the given trigger rule.

Abstract: A method for data transfer includes transmitting a sequence of data packets from a first computer over a network to a second computer in a single RDMA data transfer transaction. Upon receipt of a second packet in the sequence without previously having received the first packet, the second computer sends a NAK packet over the network to the first computer, indicating that the first packet was not received. A retransmission mode is selected responsively to the type of the transaction, such that when the transaction is of a first type, the first packet is retransmitted from the first computer to the second computer in response to the NAK packet without retransmitting the second packet, and when the transaction is of a second type, both the first and second packets are retransmitted from the first computer to the second computer in response to the NAK packet.

Abstract: A method for data communication includes submitting from a host processor to a network interface controller (NIC) during a first time period first work items instructing the NIC to transmit over a network packets containing respective data. The first work items include pointer-based work items, which contain a pointer to the respective data in a memory of the host processor, and inline work items, which contain the respective data. The performance of the NIC is measured in transmitting the packets during the first time period. During a second time period, subsequent to the first time period, the host processor submits second work items to the NIC while deciding automatically, under control of software running on the host processor and based on the measured performance during the first time period, how many of the second work items are to be pointer-based and how many are to be inline work items.

Abstract: A method for data communication includes submitting from a host processor to a network interface controller (NIC) during a first time period first work items instructing the NIC to transmit over a network packets containing respective data. The first work items include pointer-based work items, which contain a pointer to the respective data in a memory of the host processor, and inline work items, which contain the respective data. The performance of the NIC is measured in transmitting the packets during the first time period. During a second time period, subsequent to the first time period, the host processor submits second work items to the NIC while deciding automatically, under control of software running on the host processor and based on the measured performance during the first time period, how many of the second work items are to be pointer-based and how many are to be inline work items.