Abstract: A plurality of packets are received at a receiver. The plurality of packets are sent in a first ordering from a transmitter and received in a second ordering. The second ordering is different from the first ordering. The packets, when they were sent, are assigned sequence numbers based on the first ordering. As each of the plurality of packets is received in the second ordering, a packet is written to a buffer position in a buffer based on the sequence number associated with the packet. The writes to the buffer positions are out of order or in a non-sequential order as compared to a sequential ordering of buffer positions in the buffer. Packets are then read from the buffer in a sequential order. As packets are read from the buffer, they are read in the first ordering that the packets were sent in.

Abstract: A receiver for recovering a serial clock of a transmitter is provided. The receiver comprises a buffer configured to store packets received from the transmitter. The packets may be sent through a packet switched network that may incur packet delay during transmission through the network. A memory controller is configured to determine a fill level of the buffer. A frequency generator is configured to generate a clock frequency, where the frequency is used to determine when to read packets from the buffer. A frequency controller is configured to instantaneously adjust the frequency of the frequency generator based on an algorithm that determines the clock frequency based on the fill level of the buffer. Accordingly, by adjusting the frequency outputted by the frequency generator, the frequency controller is able to recover the serial clock of the transmitter.

Abstract: A system for recovering and aligning synchronous data transmissions is disclosed. The system includes a transmitter configured to transmit a source clock signal and a number of data groups over a number of channels with different latencies/propagation delays. The data groups are transmitted during the same clock cycle pursuant to the source clock signal. Each data group is transmitted over a corresponding media channel. The system also includes a receiver configured to receive the source clock signal and the data groups over the corresponding channels and to re-align or recover the wide word that comes in on the channels that are skewed.