Abstract: According to implementations of the subject matter described herein, there is proposed a solution for supporting communications for an FPGA device. In an implementation, the FPGA device includes an application module and protocol stack modules. The protocol stack modules are operable to access target devices based on different communication protocols via a physical interface. The FPGA device further includes a universal access module operable to receive, from the application module, first data and a first identity of a first target device, the first target device acting as a destination of the first data, and transmit, based on the first identity and predetermined first routing information, the first data to a first protocol stack module accessible to the first target device via the physical interface. By introducing the universal access module, it is possible to provide unified and direct communications for the application module.

Abstract: According to implementations of the subject matter described herein, there is proposed a solution for supporting communications for an FPGA device. In an implementation, the FPGA device includes an application module and protocol stack modules. The protocol stack modules are operable to access target devices based on different communication protocols via a physical interface. The FPGA device further includes a universal access module operable to receive, from the application module, first data and a first identity of a first target device, the first target device acting as a destination of the first data, and transmit, based on the first identity and predetermined first routing information, the first data to a first protocol stack module accessible to the first target device via the physical interface. By introducing the universal access module, it is possible to provide unified and direct communications for the application module.

Abstract: In accordance with implementations of the subject matter described herein, there is provided a solution for streaming communication between devices. In this solution, a memory of a first device comprising a ring buffer is allocated to be dedicated for storing a data stream of an application to be transmitted to a second electronic device. The application of the first device writes data to be transmitted into the ring buffer, to form a portion of the first data stream, and a write pointer of the ring buffer is thus updated. A portion of data is read based on a source memory address from the ring buffer via the interface device. The interface device also transmits the data portion to a second device. The read data portion is stored in a dedicated ring buffer of the memory. In accordance with the solution, an efficient streaming communication interface is provided between devices.

Abstract: According to implementations of the subject matter described herein, there is proposed a solution for supporting communications for an FPGA device. In an implementation, the FPGA device includes an application module and protocol stack modules. The protocol stack modules are operable to access target devices based on different communication protocols via a physical interface. The FPGA device further includes a universal access module operable to receive, from the application module, first data and a first identity of a first target device, the first target device acting as a destination of the first data, and transmit, based on the first identity and predetermined first routing information, the first data to a first protocol stack module accessible to the first target device via the physical interface. By introducing the universal access module, it is possible to provide unified and direct communications for the application module.

Abstract: According to implementations of the subject matter described herein, there is proposed a solution for supporting communications for an FPGA device. In an implementation, the FPGA device includes an application module and protocol stack modules. The protocol stack modules are operable to access target devices based on different communication protocols via a physical interface. The FPGA device further includes a universal access module operable to receive, from the application module, first data and a first identity of a first target device, the first target device acting as a destination of the first data, and transmit, based on the first identity and predetermined first routing information, the first data to a first protocol stack module accessible to the first target device via the physical interface. By introducing the universal access module, it is possible to provide unified and direct communications for the application module.

Abstract: The implementations of the subject matter described herein relate to communication between field programmable gate arrays. In some implementations, an FPGA device comprises a first protocol stack configured to: receive, from a source application, a data transmitting request for a destination application; package the data transmitting request into a first packet by adding a header to the data transmitting request, the header indicating the source application and the destination application; and transmit a physical address of a second protocol stack connected with the destination application. The FPGA device further comprises a PCIe interface configured to: package the first packet into a second packet based on the physical address of the second protocol stack received from the first protocol stack so that the first packet serves as a data portion of the second packet, the second packet being a TLP conforming to the PCIe standard; and transmit the second packet.

Abstract: According to implementations of the subject matter described herein, there is proposed a solution for supporting communications for an FPGA device. In an implementation, the FPGA device includes an application module and protocol stack modules. The protocol stack modules are operable to access target devices based on different communication protocols via a physical interface. The FPGA device further includes a universal access module operable to receive, from the application module, first data and a first identity of a first target device, the first target device acting as a destination of the first data, and transmit, based on the first identity and predetermined first routing information, the first data to a first protocol stack module accessible to the first target device via the physical interface. By introducing the universal access module, it is possible to provide unified and direct communications for the application module.

Abstract: The implementations of the subject matter described herein relate to communication between field programmable gate arrays. In some implementations, an FPGA device comprises a first protocol stack configured to: receive, from a source application, a data transmitting request for a destination application; package the data transmitting request into a first packet by adding a header to the data transmitting request, the header indicating the source application and the destination application; and transmit a physical address of a second protocol stack connected with the destination application. The FPGA device further comprises a PCIe interface configured to: package the first packet into a second packet based on the physical address of the second protocol stack received from the first protocol stack so that the first packet serves as a data portion of the second packet, the second packet being a TLP conforming to the PCIe standard; and transmit the second packet.

Abstract: A switch comprising a plurality of inductors and a plurality of shunt transistors is described. Each inductor can be electrically coupled between adjacent shunt transistors to form a distributed switch structure. At least two inductors in the plurality of inductors can be inductively coupled with each other. The plurality of inductors can correspond to portions of a coupling inductor, wherein the coupling inductor can have an irregular octagonal shape.

Abstract: A switch comprising a plurality of inductors and a plurality of shunt transistors is described. Each inductor can be electrically coupled between adjacent shunt transistors to form a distributed switch structure. At least two inductors in the plurality of inductors can be inductively coupled with each other. The plurality of inductors can correspond to portions of a coupling inductor, wherein the coupling inductor can have an irregular octagonal shape.