Patents by Inventor Ran Shu

Ran Shu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11451066
    Abstract: Provided are a control method and a device for active power of a wind power plant cluster. The wind power plant cluster includes wind power plants of m priorities, wherein m is a positive integer. The control method includes: monitoring the consumption capability of a power grid in real time, and determining object active power of the wind power plant cluster according to the consumption capability of the power grid; determining a command active power of the wind power plant within each priority according to the object active power of the wind power plant cluster in a descending order of the priorities; and controlling real active power of the wind power plant within each priority according to the command active power.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: September 20, 2022
    Inventors: Jingran Wang, Bingxu Zhai, Rongfu Sun, Haibo Lan, Ruoyang Wang, Ran Ding, Haixiang Xu, Zhifeng Liang, Tao Lun, Zongxiang Lu, Chen Xu, Li Shu, Yu Shen, Xiaobo Wu
  • Publication number: 20220217098
    Abstract: In accordance with implementations of the subject matter described herein, there is provided a solution for streaming communication between devices. In this solution, a memory of a first device comprising a ring buffer is allocated to be dedicated for storing a data stream of an application to be transmitted to a second electronic device. The application of the first device writes data to be transmitted into the ring buffer, to form a portion of the first data stream, and a write pointer of the ring buffer is thus updated. A portion of data is read based on a source memory address from the ring buffer via the interface device. The interface device also transmits the data portion to a second device. The read data portion is stored in a dedicated ring buffer of the memory. In accordance with the solution, an efficient streaming communication interface is provided between devices.
    Type: Application
    Filed: April 2, 2020
    Publication date: July 7, 2022
    Inventors: Zhixiong Niu, Ran Shu, Lei Qu, Peng Chen, Yongqiang Xiong, Guo Chen
  • Publication number: 20220206979
    Abstract: According to implementations of the subject matter described herein, there is proposed a solution for supporting communications for an FPGA device. In an implementation, the FPGA device includes an application module and protocol stack modules. The protocol stack modules are operable to access target devices based on different communication protocols via a physical interface. The FPGA device further includes a universal access module operable to receive, from the application module, first data and a first identity of a first target device, the first target device acting as a destination of the first data, and transmit, based on the first identity and predetermined first routing information, the first data to a first protocol stack module accessible to the first target device via the physical interface. By introducing the universal access module, it is possible to provide unified and direct communications for the application module.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 30, 2022
    Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Peng CHENG, Ran SHU, Guo CHEN, Yongqiang XIONG, Jiansong ZHANG, Ningyi XU, Thomas MOSCIBRODA
  • Patent number: 11243901
    Abstract: According to implementations of the subject matter described herein, there is proposed a solution for supporting communications for an FPGA device. In an implementation, the FPGA device includes an application module and protocol stack modules. The protocol stack modules are operable to access target devices based on different communication protocols via a physical interface. The FPGA device further includes a universal access module operable to receive, from the application module, first data and a first identity of a first target device, the first target device acting as a destination of the first data, and transmit, based on the first identity and predetermined first routing information, the first data to a first protocol stack module accessible to the first target device via the physical interface. By introducing the universal access module, it is possible to provide unified and direct communications for the application module.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: February 8, 2022
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Peng Cheng, Ran Shu, Guo Chen, Yongqiang Xiong, Jiansong Zhang, Ningyi Xu, Thomas Moscibroda
  • Patent number: 11042497
    Abstract: The implementations of the subject matter described herein relate to communication between field programmable gate arrays. In some implementations, an FPGA device comprises a first protocol stack configured to: receive, from a source application, a data transmitting request for a destination application; package the data transmitting request into a first packet by adding a header to the data transmitting request, the header indicating the source application and the destination application; and transmit a physical address of a second protocol stack connected with the destination application. The FPGA device further comprises a PCIe interface configured to: package the first packet into a second packet based on the physical address of the second protocol stack received from the first protocol stack so that the first packet serves as a data portion of the second packet, the second packet being a TLP conforming to the PCIe standard; and transmit the second packet.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: June 22, 2021
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Peng Cheng, Ran Shu, Guo Chen, Yongqiang Xiong, Jiansong Zhang, Ningyi Xu, Thomas Moscibroda
  • Publication number: 20200167302
    Abstract: According to implementations of the subject matter described herein, there is proposed a solution for supporting communications for an FPGA device. In an implementation, the FPGA device includes an application module and protocol stack modules. The protocol stack modules are operable to access target devices based on different communication protocols via a physical interface. The FPGA device further includes a universal access module operable to receive, from the application module, first data and a first identity of a first target device, the first target device acting as a destination of the first data, and transmit, based on the first identity and predetermined first routing information, the first data to a first protocol stack module accessible to the first target device via the physical interface. By introducing the universal access module, it is possible to provide unified and direct communications for the application module.
    Type: Application
    Filed: April 24, 2018
    Publication date: May 28, 2020
    Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Peng CHENG, Ran SHU, Guo CHEN, Yongqiang XIONG, Jiansong ZHANG, Ningyi XU, Thomas MOSCIBRODA
  • Publication number: 20200117630
    Abstract: The implementations of the subject matter described herein relate to communication between field programmable gate arrays. In some implementations, an FPGA device comprises a first protocol stack configured to: receive, from a source application, a data transmitting request for a destination application; package the data transmitting request into a first packet by adding a header to the data transmitting request, the header indicating the source application and the destination application; and transmit a physical address of a second protocol stack connected with the destination application. The FPGA device further comprises a PCIe interface configured to: package the first packet into a second packet based on the physical address of the second protocol stack received from the first protocol stack so that the first packet serves as a data portion of the second packet, the second packet being a TLP conforming to the PCIe standard; and transmit the second packet.
    Type: Application
    Filed: April 25, 2018
    Publication date: April 16, 2020
    Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Peng CHENG, Ran SHU, Guo CHEN, Yongqiang XIONG, Jiansong ZHANG, Ningyi XU, Thomas MOSCIBRODA
  • Patent number: 9621152
    Abstract: A switch comprising a plurality of inductors and a plurality of shunt transistors is described. Each inductor can be electrically coupled between adjacent shunt transistors to form a distributed switch structure. At least two inductors in the plurality of inductors can be inductively coupled with each other. The plurality of inductors can correspond to portions of a coupling inductor, wherein the coupling inductor can have an irregular octagonal shape.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: April 11, 2017
    Assignees: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Ran Shu, Adrian J. Tang, Qun Gu, Brian J. Drouin
  • Publication number: 20160336934
    Abstract: A switch comprising a plurality of inductors and a plurality of shunt transistors is described. Each inductor can be electrically coupled between adjacent shunt transistors to form a distributed switch structure. At least two inductors in the plurality of inductors can be inductively coupled with each other. The plurality of inductors can correspond to portions of a coupling inductor, wherein the coupling inductor can have an irregular octagonal shape.
    Type: Application
    Filed: May 13, 2016
    Publication date: November 17, 2016
    Inventors: Ran Shu, Adrian J. Tang, Qun Gu, Brian J. Drouin