Patents by Inventor Ran Ye

Ran Ye has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11894458
    Abstract: A lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS), including: a trench gate including a lower part inside a trench and an upper part outside the trench, a length of the lower part in a width direction of a conducting channel being less than that of the upper part, and the lower part extending into a body region and having a depth less than that of the body region; an insulation structure arranged between a drain region and the trench gate and extending downwards into a drift region, a depth of the insulation structure being less than that of the drift region.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: February 6, 2024
    Assignees: SOUTHEAST UNIVERSITY, CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Jiaxing Wei, Qichao Wang, Kui Xiao, Dejin Wang, Li Lu, Ling Yang, Ran Ye, Siyang Liu, Weifeng Sun, Longxing Shi
  • Publication number: 20230019004
    Abstract: A lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS), including: a trench gate including a lower part inside a trench and an upper part outside the trench, a length of the lower part in a width direction of a conducting channel being less than that of the upper part, and the lower part extending into a body region and having a depth less than that of the body region; an insulation structure arranged between a drain region and the trench gate and extending downwards into a drift region, a depth of the insulation structure being less than that of the drift region.
    Type: Application
    Filed: September 25, 2020
    Publication date: January 19, 2023
    Inventors: Jiaxing WEI, Qichao WANG, Kui XIAO, Dejin WANG, Li LU, Ling YANG, Ran YE, Siyang LIU, Weifeng SUN, Longxing SHI
  • Publication number: 20180060220
    Abstract: Techniques are provided for creating mock responses based on default data and mapping actual requests to those mock responses so that a service under test (SUT) may be executed within a simulated integration. In one technique, multiple example requests (ERs) that exemplify actual requests that the SUT may send during a test case are created. Each ER is configured to invoke a downstream service. For each ER, a mock downstream response that is based on default values is created. In a mapping, an association between each ER and its mock downstream response is stored. During the test, the SUT is invoked. Responsively, the SUT generates downstream requests to downstream services, regardless of actual availability. The computer intercepts each invocation of a downstream request. Based on the downstream request, the computer selects a mock downstream response from the mapping and provides the mock downstream response to the SUT.
    Type: Application
    Filed: August 23, 2016
    Publication date: March 1, 2018
    Inventors: YIDA YAO, Weizhen Wang, Ran Ye, Vakwadi Thejaswini Holla