Abstract: Floating gates are formed in two separate polysilicon depositions steps resulting in distinct portions. The first formed portions are between isolation regions. A thick insulator is formed over the isolation regions and floating gate portions. The thick insulator is patterned to leave fences over the isolation regions. A thinning process, an isotropic etch in this example, is applied to these fences to make them thinner. Polysilicon sidewall spacers are formed on the sides of these fences. These sidewall spacers become the second portion of the floating gate. These second portions have the desired shape for significantly increasing the capacitance to the subsequently formed control gates, thereby reducing the gate voltage required for programming and erasing made by a relatively robust process.

Abstract: A semiconductor device structure has trenches of two widths or more. The smallest widths are to maximize density. The greater widths may be required because of more demanding isolation, for example, in the case of non-volatile memories. These more demanding, wider isolation trenches are lined with a high quality grown oxide as part of the process for achieving the desired result of high quality isolation. For the case of the narrowest trenches, the additional liner causes the aspect ratio, the ratio of the depth of the trench to the width of the trench, to increase. Subsequent deposition of insulating material to fill the trenches with the highest aspect ratios can result in voids that can ultimately result in degraded yields. These voids are avoided by etching at least a portion of the liners of those trenches with the highest aspect ratios to reduce the aspect ratio to acceptable levels.

Abstract: A semiconductor device has recesses formed in the substrate during removal of the anti-reflective coating (ARC) because these recess locations are exposed during the etching of the ARC. Although the etchant is chosen to be selective between the ARC material and the substrate material, this selectivity is limited so that recesses do occur. A problem associated with the formation of these recesses is that the source/drains have further to diffuse to become overlapped with the gate. The result is that the transistors may have reduced current drive. The problem is avoided by waiting to perform the ARC removal until at least after formation of a sidewall spacer around the gate. The consequent recess formation thus occurs further from the gate, which results in reducing or eliminating the impediment this recess can cause to the source/drain diffusion that desirably extends to overlap with the gate.

Abstract: A method for achieving a uniform planar surface by a chemical mechanical polish includes surrounding an active area or array to be polished with a border of the active material such that the border is wider than a single active area within the array and is preferably spaced from the outermost active area by the same distance as the distance between active areas within the array.

Abstract: A semiconductor device has recesses formed in the substrate during removal of the anti-reflective coating (ARC) because these recess locations are exposed during the etching of the ARC. Although the etchant is chosen to be selective between the ARC material and the substrate material, this selectivity is limited so that recesses do occur. A problem associated with the formation of these recesses is that the source/drains have further to diffuse to become overlapped with the gate. The result is that the transistors may have reduced current drive. The problem is avoided by waiting to perform the ARC removal until at least after formation of a sidewall spacer around the gate. The consequent recess formation thus occurs further from the gate, which results in reducing or eliminating the impediment this recess can cause to the source/drain diffusion that desirably extends to overlap with the gate.

Abstract: A semiconductor device has recesses formed in the substrate during removal of the anti-reflective coating (ARC) because these recess locations are exposed during the etching of the ARC. Although the etchant is chosen to be selective between the ARC material and the substrate material, this selectivity is limited so that recesses do occur. A problem associated with the formation of these recesses is that the source/drains have further to diffuse to become overlapped with the gate. The result is that the transistors may have reduced current drive. The problem is avoided by waiting to perform the ARC removal until at least after formation of a sidewall spacer around the gate. The consequent recess formation thus occurs further from the gate, which results in reducing or eliminating the impediment this recess can cause to the source/drain diffusion that desirably extends to overlap with the gate.

Abstract: A semiconductor device structure has trenches of two widths or more. The smallest widths are to maximize density. The greater widths may be required because of more demanding isolation, for example, in the case of non-volatile memories. These more demanding, wider isolation trenches are lined with a high quality grown oxide as part of the process for achieving the desired result of high quality isolation. For the case of the narrowest trenches, the additional liner causes the aspect ratio, the ratio of the depth of the trench to the width of the trench, to increase. Subsequent deposition of insulating material to fill the trenches with the highest aspect ratios can result in voids that can ultimately result in degraded yields. These voids are avoided by etching at least a portion of the liners of those trenches with the highest aspect ratios to reduce the aspect ratio to acceptable levels.

Abstract: A semiconductor device has both a logic section and a non-volatile memory (NVM) section. Transistors in both sections are separated by trench isolation. The logic isolation has narrower trenches than NVM trenches and both types of trenches have corners at the tops thereof. The trenches are lined by growing an oxide that is necessarily to take care of the plasma damage of the substrate, which is preferably silicon, that occurs during the formation of the trenches. These oxide liners are grown to a greater thickness in the NVM trenches than in the logic trenches to obtain a greater degree of corner rounding in the NVM trenches. This growth differential is achieved by selectively implanting the NVM trenches with a species that speeds oxide growth or selectively implanting the logic trenches with a species that retards oxide growth. As a further alternative, the NVM trenches can be implanted with a growth enhancing species and the logic trenches with a retarding species.

Abstract: Semiconductor devices and processes for forming the same. The semiconductor device includes field isolation regions within trenches lying within a semiconductor device substrate. The trenches include a first trench and a second trench. The device includes a first component region and a second component region. The first component region lies near the first trench, and the second component region lies near the second trench. The semiconductor device includes a feature selected from a group consisting of: (a) a first liner within the first trench, and a second liner within the second trench, wherein the first liner is significantly thicker than the second liner; and (b) the first component region has a first edge with a first radius of curvature near the first trench, and the second component has a second edge with a second radius of curvature near the second trench, wherein the first radius of curvature is significantly greater than the second radius of curvature.

Abstract: A method for achieving a uniform planar surface by a chemical mechanical polish includes surrounding an active area or array to be polished with a border of the active material such that the border is wider than a single active area within the array and is preferably spaced from the outermost active area by the same distance as the distance between active areas within the array.

Abstract: A method for achieving a uniform planar surface by a chemical mechanical polish includes surrounding an active area or array to be polished with a border of the active material such that the border is wider than a single active area within the array and is preferably spaced from the outermost active area by the same distance as the distance between active areas within the array.

Abstract: A method for producing a uniform metal coating on a substrate consisting of (1) selecting one or more metals to be coated onto the substrate wherein the metals are soluble in a molten salt when heated, (2) preparing a bath consisting of the dissolved metal-molten salt, (3) inserting a substrate into the bath, and (4) decreasing the temperature at the substrate to a level at which the metal will precipitate out of solution onto the substrate. Multiple coatings can be made by repeating the method using the same or different metal-molten salt systems. Deposition can be enhanced by adding more salt to the bath to increase precipitation of the metal onto the substrate or by introducing additional metal into the bath by electrolysis, either by electrowinning or electrorefining. The metal coating can be patterned by localized heating of the metal coating in the metal-molten salt bath to reverse deposition or by masking areas on the substrate prior to deposition.