Abstract: A package comprising a substrate; a first integrated device coupled to the substrate through at least a first plurality of solder interconnects; a first encapsulation layer at least partially encapsulating the first integrated device; a plurality of through molding encapsulation layer via interconnects located in the first encapsulation layer; wherein the plurality of through molding encapsulation layer via interconnects are configured to provide an electrical path for ground; a seed layer coupled to and touching the first encapsulation layer, the plurality of through molding encapsulation layer via interconnects and a back side of the first integrated device; and a first heat sink coupled to the seed layer.

Abstract: A package comprising a substrate; a first integrated device coupled to the substrate through at least a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated device, wherein the encapsulation layer includes a cavity; a metallization portion coupled to the first integrated device; and a first passive device coupled to the metallization portion through at least a second plurality of solder interconnects, wherein the first passive device is located at least partially in the cavity of the encapsulation layer.

Abstract: A package comprising a substrate; a first integrated device coupled to the substrate through at least a first plurality of solder interconnects; a first encapsulation layer at least partially encapsulating the first integrated device, wherein the first encapsulation layer includes a cavity; a plurality of through encapsulation layer via interconnects located in the first encapsulation layer; a metallization portion coupled to the plurality of through encapsulation layer via interconnects; and a second integrated device coupled to the metallization portion through at least a second plurality of solder interconnects, wherein the second integrated device is located at least partially in the cavity of the first encapsulation layer.

Abstract: A device includes a resonator stack. The resonator stack includes a first chiplet including a first acoustic resonator having a first resonant frequency and a second chiplet including a second acoustic resonator having a second resonant frequency that is different from the first resonant frequency. The device also includes a substrate coupled to the resonator stack, and electrical interconnections between the first chiplet and the second chiplet to provide a conductive path between the first acoustic resonator and the second acoustic resonator.

Abstract: An apparatus includes a substrate that includes a first integrated inductor. The first integrated inductor includes a first core material disposed within a first cavity of the substrate. The first integrated inductor also includes a first set of conductive windings that at least partially encircle the first core material within the first cavity.

Abstract: Disclosed are examples of multi-die modules that includes a die (e.g., a power amplifier) and an adjacent die placed side-by-side and bonded onto a substrate with a mold compound. The die (e.g., a switch or a low noise amplifier) may be double EMI shielded to minimize or even eliminate EMI/noise coupling with the adjacent die (e.g., switch, low noise amplifier, etc.). Another mold compound, which can be thermally conductive, may be provided to improve transfer of heat away from the die and/or the adjacent die.

Abstract: Various aspects of the present disclosure generally relate to a bonding pad configuration. A device includes a die including multiple bonding pads, pad configuration circuitry, and control circuitry. The pad configuration circuitry is configured to, based on a routing configuration, selectively connect multiple nodes of first circuitry to a first set of bonding pads of the multiple bonding pads. The control circuitry is connected to the pad configuration circuitry and configured to obtain the routing configuration.

Abstract: An antenna module as a radio-frequency (RF) integrated circuit (IC) semiconductor die (“die”) with an integrated antenna substrate. The die with the integrated antenna substrate can be provided as part of a single IC chip that is fabricated as part of a wafer-level fabrication process as an example. The antenna elements are formed in one more antenna layers as part of an antenna substrate. The antenna layers may be formed as re-distribution layers (RDLs) for example to support smaller line-spacing (LS) and/or smaller pitched metal interconnects for forming and interconnecting to smaller wavelength antenna elements for supporting higher frequency communications. The antenna substrate is formed on a semiconductor wafer of an IC as part of the die. In this manner, the antenna layers can be formed as part of a wafer-level fabrication process used to form the die to form the antenna layers.

Abstract: A device comprising a substrate; an opto-electronic integrated device coupled to the substrate; a first integrated device coupled to the substrate through a first plurality of solder interconnects; and a second integrated device coupled to the first integrated device through a second plurality of solder interconnects.

Abstract: Aspects disclosed in the detailed description include an impure Indium Phosphide (InP) semiconductor substrate. Related apparatus and methods are also disclosed. In this regard, in some exemplary aspects disclosed herein, a semiconductor substrate comprising a silicon layer and an impure InP layer adjacent to the silicon layer. The impure InP layer may be epitaxially grown on a Silicon (Si) nanoridge base or directly bonded to the silicon layer after being epitaxially grown and cleaved. Utilizing an impure InP layer advantageously provides structural strength to be deployed in a 300 millimeter wafer process while achieving the electrical and thermal characteristic of InP it provides in a semiconductor substrate.

Abstract: An integrated circuit (IC) includes a substrate and a first through substrate via (TSV) in the substrate. The first TSV includes a first metal-insulator-metal (MIM) capacitor. The first MIM capacitor includes a first plate composed of a first metallization layer on an inner surface of the first TSV. The first MIM capacitor includes a MIM insulator layer on the first plate. The first MIM capacitor includes a second plate composed of a second metallization layer on the MIM insulator layer. The IC includes a 3D inductor. The 3D inductor includes a second TSV in the substrate. The 3D inductor includes a first trace on a first surface of the substrate, coupled to a first end of the second TSV. The 3D inductor further includes a second trace on a second surface of the substrate and coupled to a second end of the second TSV and a second end of the first TSV.

Abstract: A multi-chip package includes a first chiplet including power amplifier (PA) circuitry. The multi-chip package also includes a second chiplet including low-noise amplifier (LNA) circuitry. The multi-chip package further includes an electromagnetic interference (EMI) shield between the first chiplet and the second chiplet. The multi-chip package also includes mold compound at least partially encapsulating the first chiplet, the second chiplet, and the EMI shield.

Abstract: An apparatus is disclosed for reducing parasitic capacitance. In an example aspect, an apparatus includes an amplifier having a differential cascode configuration. Each stack of the amplifier includes a first transistor configured to operate as an input stage and a second transistor configured to operate as a cascode stage. The first and second transistors each include two channel terminal regions having a doping type that is uniform across the two channel terminal regions. Surfaces of first channel terminal regions of the first and second transistors abut a first and second quantity of electrical contacts, respectively. Second channel terminal regions of the first and second transistors form a floating region at a floating node. Each of the first quantity of electrical contacts and the second quantity of electrical contacts is greater than a third quantity of electrical contacts abutting a surface of the floating region.

Abstract: A device includes a resonator stack. The resonator stack includes a first chiplet including a first acoustic resonator having a first resonant frequency and a second chiplet including a second acoustic resonator having a second resonant frequency that is different from the first resonant frequency. The device also includes a substrate coupled to the resonator stack, and electrical interconnections between the first chiplet and the second chiplet to provide a conductive path between the first acoustic resonator and the second acoustic resonator.

Abstract: A packaged integrated circuit device includes a die that includes integrated radio frequency (RF) circuitry. The packaged integrated circuit device also includes a package substrate including metal layers electrically connected to the RF circuitry. The packaged integrated circuit device further includes an impedance adapter electrically connected to the RF circuitry and disposed between the die and the package substrate. The impedance adapter includes a passive component disposed on or in a body of the impedance adapter.

Abstract: An interposer has a first side and a second side and includes an optical waveguide defined in a region between the first side and the second side. The interposer also includes first contacts on the first side configured to be electrically connected to one or more electronic devices, and second contacts on the second side configured to be electrically connected to one or more photonic devices. The interposer also includes conductive interconnects electrically connecting one or more of the first contacts to one or more of the second contacts. The interposer also includes an optical coupler on the second side configured to enable coupling of light between the one or more photonic devices and the optical waveguide.

Abstract: Antenna modules employing three-dimensional (3D) build-up on mold package to support efficient integration of radio-frequency (RF) circuitry, and related fabrication methods. The antenna module includes a RF transceiver whose circuitry is split over multiple semiconductor dies (“dies”) so different semiconductor devices can be formed in different semiconductor structures. The antenna module is provided as a 3D build-up on mold package to reduce lengths of die-to-die (D2D) interconnections between circuits in different dies. First and second die packages that include respective first and second dies encapsulated in respective first and second mold layers are coupled to each other in a vertical direction in a 3D stacked arrangement with active faces of the first and second dies facing each other to provide a reduced distance between the active faces of the first and second dies. An antenna is stacked on the second die package to provide an antenna(s) for the antenna module.

Abstract: A device includes a die that includes a set of contacts coupled to a first side of the die. The die also includes active circuitry coupled to the set of contacts. The device also includes a thermal interposer layer (TIL) adjacent to the first side of the die. The TIL includes a thermally conductive material having one or more though hole vias (THVs) aligned with one or more first contacts of the set of contacts. The device further includes a set of conductive connectors that are coupled to the one or more first contacts and that extend through the THVs.

Abstract: A substrate that includes an encapsulation layer, a first acoustic resonator, a second acoustic resonator, at least one first dielectric layer, a plurality of first interconnects, at least one second dielectric layer, and a plurality of second interconnects. The first acoustic resonator is located in the encapsulation layer. The first acoustic resonator includes a first piezoelectric substrate comprising a first thickness. The second acoustic is located in the encapsulation layer. The second acoustic resonator includes a second piezoelectric substrate comprising a second thickness that is different than the first thickness. The at least one first dielectric layer is coupled to a first surface of the encapsulation layer. The plurality of first interconnects is coupled to the first surface of the encapsulation layer. The plurality of first interconnects is located at least in the at least one first dielectric layer.

Abstract: A three dimensional (3D) inductor is described. The 3D inductor includes a first plurality of micro-through substrate vias (TSVs) within a first area of a substrate. The 3D inductor also includes a first trace on a first surface of the substrate, coupled to a first end of the first plurality of micro-TSVs. The 3D inductor further includes a second trace on a second surface of the substrate, opposite the first surface, coupled to a second end, opposite the first end, of the first plurality of micro-TSVs.