Abstract: A radio frequency (RF) validator instrument is provided for testing functionality of a test article. The instrument includes an RF transmitter, a connection apparatus, an RF receiver, a direct current (DC) bias detector, and an RF verifier. The transmitter produces an emission signal supplied to an in-port and an out-port. The apparatus connects the in-port and the out-port to separate terminals of the article. The receiver receives said emission signal and producing a detection signal. The DC bias detector receives the emission signal through the out-port to a first voltage divider as a first bias signal, through the in-port to a second voltage divider as a second bias signal, and combining the first and second bias signals as a combination bias signal. The verifier compares the detection and combination bias signals to determine whether the article satisfies functionality.

Abstract: A digital camera system includes a digital image sensor, a memory coupled to the digital image sensor via a data bus, a microcontroller having control signal output ports and a data I/O port, and a bi-directional tri-state buffer coupled to the data I/O port and the data bus for passing data therebetween. At least one of the control signal output ports is coupled to each of the digital image sensor, memory and tri-state buffer. The microcontroller issues control signals over it's control signal output ports to control access to the data bus by establishing only one of a plurality of possible data transfer paths at any given point in time.

Abstract: A digital camera system includes a digital image sensor, a memory coupled to the digital image sensor via a data bus, a microcontroller having control signal output ports and a data I/O port, and a bi-directional tri-state buffer coupled to the data I/O port and the data bus for passing data therebetween. At least one of the control signal output ports is coupled to each of the digital image sensor, memory and tri-state buffer. The microcontroller issues control signals over it's control signal output ports to control access to the data bus by establishing only one of a plurality of possible data transfer paths at any given point in time.