Abstract: A set of physical input/output adapters (PIOAs) is configured such that each PIOAs in the set of PIOAs is a functional equivalent of another PIOAs in the set of PIOAs. A utilization of each PIOA in the set of PIOAs is measured. A number of PIOAs needed to service a workload is determined. A first subset of PIOAs from the set of PIOAs is powered down if the number of PIOAs needed to service the workload is smaller than a number of operational PIOAs. The I/O operations associated with the first subset of PIOAs are transferred to a second subset of PIOAs remaining operational in the set of PIOAs.

Abstract: An approach identifies an amount of high order bits used to store a memory address in a memory address field that is included in a memory. This approach calculates at least one minimum number of low order bits not used to store the address with the calculation being based on the identified amount of high order bits. The approach retrieves a data element from one of the identified minimum number of low order bits of the address field and also retrieves a second data element from one of the one of the identified minimum number of low order bits of the address field.

Abstract: A system, and computer usable program product for expanding memory size are provided in the illustrative embodiments. A desired size of an expanded memory and a first information about a workload in the data processing system are received. A size of a compressed memory pool to use with the memory to make the desired size of the expanded memory available is computed. A representation of the memory is configured, the representation of the memory appearing to be of a size larger than the size of the memory, the representation of the memory being the expanded memory, and the size of the representation being the size of the expanded memory. The expanded memory is made available such that the memory in the data processing system is usable by addressing the expanded memory.

Abstract: A method, system, and computer usable program product for scaling energy use in a virtualized data processing environment are provided in the illustrative embodiments. A set of PIOAs is configured such that each PIOAs in the set of PIOAs is a functional equivalent of another PIOAs in the set of PIOAs. A utilization of each PIOA in the set of PIOAs is measured. A number of PIOAs needed to service a workload is determined. A first subset of PIOAs from the set of PIOAs is powered down if the number of PIOAs needed to service the workload is smaller than a number of operational PIOAs. The I/O operations associated with the first subset of PIOAs are transferred to a second subset of PIOAs remaining operational in the set of PIOAs.

Abstract: A mechanism is provided in a logically partitioned data processing system for controlling depth and latency of exit of a virtual processor's idle state. A virtualization layer generates a cede latency setting information (CLSI) data. Responsive to booting a logical partition, the virtualization layer communicates the CLSI data to an operating system (OS) of the logical partition. The OS determines, based on the CLSI data, a particular idle state of a virtual processor under a control of the OS. Responsive to the OS calling the virtualization layer, the OS communicates the particular idle state of the virtual processor to the virtualization layer for assigning the particular idle state and wake-up characteristics to the virtual processor.

Abstract: A method, apparatus, and computer program product are disclosed for dynamically determining when to yield a processor that is assigned to perform particular work but that is currently idle. A particular processor is assigned to perform work. A determination is made regarding whether the processor is currently idle. If the processor is currently idle, a determination is made of a length of time the processor has been idle. If this determined length of time exceeds a self-tunable threshold, the processor is yielded to make the processor available to perform other work. The threshold can be dynamically tuned during runtime.

Abstract: An approach identifies an amount of high order bits used to store a memory address in a memory address field that is included in a memory. This approach calculates at least one minimum number of low order bits not used to store the address with the calculation being based on the identified amount of high order bits. The approach retrieves a data element from one of the identified minimum number of low order bits of the address field and also retrieves a second data element from one of the one of the identified minimum number of low order bits of the address field.

Abstract: A method, system, and computer usable program product for expanding memory size are provided in the illustrative embodiments. A desired size of an expanded memory and a first information about a workload in the data processing system are received. A size of a compressed memory pool to use with the memory to make the desired size of the expanded memory available is computed. A representation of the memory is configured, the representation of the memory appearing to be of a size larger than the size of the memory, the representation of the memory being the expanded memory, and the size of the representation being the size of the expanded memory. The expanded memory is made available such that the memory in the data processing system is usable by addressing the expanded memory.

Abstract: The illustrative embodiments described herein provide a computer implemented method, apparatus, and computer program product for adjusting a page size for a virtual memory range. The process identifies a set of pages in the virtual memory range that reside on a primary memory to form a page occupancy. Each of the set of pages has a first page size. The process changes the first page size to a second page size in response to a comparison of the page occupancy to a threshold value indicating that the first page size should be adjusted.

Abstract: A computer implemented method, apparatus, and computer usable program code for managing real memory. In response to a request for a page to be moved into real memory, a contiguous range of real memory is reserved for the page corresponding to a contiguous virtual memory range to form a reservation within a plurality of reservations for the real memory. This reservation enables efficient promotion of pages to a larger page size. The page only occupies a portion of the contiguous range of real memory for the reservation. In response to a need for real memory, a selected reservation is released within the plurality of reservations based on an age of the selected reservation within the plurality of reservations.

Abstract: A power level monitor and performance tracking tool are provided for correlating system performance with processor management events. When power management requires a change to the state of a microprocessor, software will be notified. Multiple layers of software may be notified, including a firmware level, an operating system, as well as applications. The performance tracking tool tracks the times of the power management events as well as their impact to the microprocessor performance. The performance tracking tool may then display or record the state changes to processor performance. These changes may be correlated against other system events to aid in determining system performance problems with respect to power management.

Abstract: According to a method of operating a data processing system, one or more monitoring parameter sets are established in a processing unit within the data processing system. The processing unit monitors, in hardware, execution of each of a plurality of schedulable software entities within the processing unit in accordance with a monitoring parameter set among the one or more monitoring parameter sets. The processing unit then reports to software executing in the data processing system utilization of hardware resources by each of the plurality of schedulable software entities. The hardware utilization information reported by the processing unit may be stored and utilized by software to schedulable execution of the schedulable software entities reported by the processing unit.

Abstract: A method, apparatus, and computer program product are disclosed for a simultaneous multithreading (SMT) data processing system for modifying the processing of software threads that acquire a contentious software lock. The system includes a processor that is capable of concurrently executing multiple different threads on the processor. The processor is also capable of utilizing hardware thread priorities assigned to each thread the processor is processing by granting a greater, disparate amount of resources to the highest priority thread. A hardware priority is assigned to each one of the SMT threads. A contentious lock is identified. Ones of the multiple threads are identified that attempt to acquire the contentious lock. These threads are dynamically redirected to special code for handling contentious locks. The hardware priority of a thread acquiring a contentious lock is then boosted.

Abstract: A computer implemented method, apparatus, and computer usable program code for managing real memory. In response to a request for a page to be moved into real memory, a contiguous range of real memory is reserved for the page corresponding to a contiguous virtual memory range to form a reservation within a plurality of reservations for the real memory. This reservation enables efficient promotion of pages to a larger page size. The page only occupies a portion of the contiguous range of real memory for the reservation. In response to a need for real memory, a selected reservation is released within the plurality of reservations based on an age of the selected reservation within the plurality of reservations.

Abstract: The illustrative embodiments described herein provide a computer implemented method, apparatus, and computer program product for adjusting a page size for a virtual memory range. The process identifies a set of pages in the virtual memory range that reside on a primary memory to form a page occupancy. Each of the set of pages has a first page size. The process changes the first page size to a second page size in response to a comparison of the page occupancy to a threshold value indicating that the first page size should be adjusted.

Abstract: Software communicates to a processing unit a classification each of at least one schedulable software entity that the processing unit executes. A resource manager within the processing unit dynamically allocates hardware resources within the processing unit to the schedulable software entity during execution in accordance with the classification. The classification may be retrieved by the software from in data storage, and operating system software may schedule the schedulable software entity for execution by reference to the classification. The processing unit may also monitor, in hardware, execution of each of a plurality of schedulable software entities within the processing unit in accordance with a monitoring parameter set. The processing unit may then report to software the utilization of hardware resources by each of the plurality of schedulable software entities so that the software may develop or refine a classification for the schedulable software entity.

Abstract: A method, apparatus, and computer program product are disclosed for dynamically determining when to yield a processor that is assigned to perform particular work but that is currently idle. A particular processor is assigned to perform work. A determination is made regarding whether the processor is currently idle. If the processor is currently idle, a determination is made of a length of time the processor has been idle. If this determined length of time exceeds a self-tunable threshold, the processor is yielded to make the processor available to perform other work. The threshold can be dynamically tuned during runtime.

Abstract: A method, apparatus, and computer program product in a shared processor data processing system are disclosed for dynamically tuning an amount of physical processor capacity that is allocated to each one of multiple logical partitions. A physical processor is shared among the logical partitions. A service window is allocated to each logical partition during each dispatch time slice. Processes that are defined by a first one of the logical partitions are executed during a first service window that was allocated to the first logical partition. A determination is made dynamically during runtime as to whether a length of the first service window should be increased to optimize interrupt processing and reduce interrupt latency. If it is determined that the length should be increased, the length of the first service window is dynamically increased during runtime.

Abstract: A virtual mode virtual memory manager method and apparatus are provided. Mechanisms are provided for allowing a virtual memory manager to operate in virtual mode utilizing virtual addresses for all of its own data structures, allowing for physical discontinuity of the physical memory backing those data structures. First order virtual memory manager metadata is included for resolving system wide virtual memory page faults. Second order virtual memory manager metadata is provided to resolve faults on the first order virtual memory manager metadata. The second order virtual memory manager metadata is associated with pinned entries in a page table and thus, faults on the second order virtual memory manager metadata cannot occur.

Abstract: A system, method, and computer program product are disclosed for invalidating specified pretranslations maintained in a data processing system which maintains decentralized copies of pretranslations. A centralized mapping of virtual addresses to their associated physical addresses is established. The centralized mapping includes a listing of pretranslations of the virtual addresses to their associated physical addresses. Multiple lists of pretranslations are generated. Control of the lists may be passed from one entity to another, such that the lists are not owned by any particular entity. Each one of the lists includes a copy of pretranslations for virtual addresses. A particular one of the physical addresses is specified. Each list that includes a pretranslation of a virtual address to the specified physical addresses is located. The pretranslation of the virtual address to the specified physical address is then invalidated within each one of the lists.