Abstract: A system can include a plurality of memory devices, wherein the plurality of memory devices includes at least three memory devices. The system can include an IC. The IC can include a memory controller coupled to each of the plurality of memory devices in parallel, wherein the memory controller is configured to broadcast a read command to each of the plurality of memory devices. The IC can include an error correction circuit coupled to each of the plurality of memory devices, wherein the error correction circuit is configured to compare data bits received from the plurality of memory devices responsive to the read command and output data bits corresponding to a majority of the data bits received from the plurality of memory devices. The IC can include a consumer circuit coupled to the error correction circuit, wherein the consumer circuit receives the data bits output from the error correction circuit.

Abstract: A circuit couples a test access port (TAP) having a JTAG interface to another port having a serial interface different from the JTAG interface. The circuit includes a forwarding circuit and a timing control circuit. The forward circuit is coupled to couple a test data in (TDI) terminal, a test data out (TDO) terminal, and a test clock (TCK) terminal of the TAP to an input terminal, an output terminal, and a clock terminal of the another port, respectively. The timing control circuit is coupled to drive a select terminal of the another port with a select signal that activates serial data transfer through the serial interface to a device. The timing control circuit delays assertion of the select signal by a configurable time period after assertion of a shift data state of a state machine of the TAP.