Patents by Inventor Randal Passint

Randal Passint has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8812765
    Abstract: A method for maintaining data coherency in a shared-memory computer system having a plurality of nodes divides the local memory of a given node into one or more blocks and stores a data record for each block indicating a plurality of node groups and a selection of the node groups. Each selected node group represents a number of nodes, and selected node groups represent at least one node that has requested access to the block. In response to receiving an access request from a requesting node that may or may not be in a selected node group, the method and system update the data record to indicate the correct selection. If the requesting node is not in any node group, the data record is adjusted to have new node groups, one of which represents the requesting node.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: August 19, 2014
    Assignee: Silicon Graphics International Corp.
    Inventors: Donglai Dai, Randal Passint
  • Publication number: 20070106850
    Abstract: A method and apparatus for maintaining data coherency in a computer system having a plurality of nodes forms a directory by grouping the nodes into a plurality of hierarchical groups of two or more levels. The method and apparatus also 1) set the directory to have data relating to a first set of groups within a first level, and 2) determine if a requesting node requesting data is a member of one of the first set of groups. The directory then is set to have data relating to a second group of nodes if the requesting node is determined not to be a member of the first set of groups within the first level. The second group of nodes is in a higher level than the first level.
    Type: Application
    Filed: November 7, 2005
    Publication date: May 10, 2007
    Applicant: Silicon Graphics, Inc.
    Inventors: Donglai Dai, Randal Passint
  • Publication number: 20060282648
    Abstract: A system and method for interconnecting a plurality of processing element nodes within a scalable multiprocessor system is provided. Each processing element node includes at least one processor and memory. A scalable interconnect network includes physical communication links interconnecting the processing element nodes in a cluster. A first set of routers in the scalable interconnect network route messages between the plurality of processing element nodes. One or more metarouters in the scalable interconnect network route messages between the first set of routers so that each one of the routers in a first cluster is connected to all other clusters through one or more metarouters.
    Type: Application
    Filed: December 6, 2005
    Publication date: December 14, 2006
    Inventors: Martin Deneroff, Gregory Thorson, Randal Passint
  • Publication number: 20060282751
    Abstract: A method and apparatus for managing X4 or larger types of memory first receives a data word to be stored in the memory, and then generates a check datum, which is a function of the data word and a set of encode data. After storing the data word in memory, the method and apparatus use the check datum and the data word to generate a syndrome. The method and apparatus then determine if the data word in the memory is correct as a function of the syndrome.
    Type: Application
    Filed: May 24, 2005
    Publication date: December 14, 2006
    Inventor: Randal Passint
  • Publication number: 20060265554
    Abstract: An apparatus and method of controlling data sharing in a shared memory computer system transfers control of a cache coherency directory (entry) to a node having control of the data. Specifically, the plurality of nodes includes a home node and a second node. The home node has given data in a cache line in its memory, and also has a directory identifying the state of the cache line. The method and apparatus thus detect a request for ownership of the cache line from the second node, and enable the second node to control the directory after receipt of the request.
    Type: Application
    Filed: April 28, 2006
    Publication date: November 23, 2006
    Inventors: John Carter, Randal Passint, Liqun Cheng, Donglai Dai
  • Publication number: 20060242308
    Abstract: A method and apparatus for controlling access by a set of accessing nodes to memory of a home node (in a multimode computer system) determines that each node in the set of nodes has accessed the memory, and forwards a completion message to each node in the set of nodes after it is determined that each node has accessed the memory. The completion message has data indicating that each node in the set of nodes has accessed the memory of the home node.
    Type: Application
    Filed: April 25, 2005
    Publication date: October 26, 2006
    Inventors: John Carter, Randal Passint, Donglai Dai, Zhen Fang, Lixin Zhang, Gregory Thorson