Patents by Inventor Randall Bach

Randall Bach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7106073
    Abstract: The present invention is directed to a system for area efficient charge-based capacitance measurement requiring a minimum silicon area for probe pads. A structure block for the system includes several test structures coupled to a target test capacitance structure, a reference structure, and a logic block. Each test structure is coupled to a corresponding test capacitance structure. The logic block coupled to the several test structures selects a desirable test structure from the several test structures. The system may include several structure blocks and an additional logic block to select a desirable structure block. Each structure block includes a single output pin for busing each test output from the several test structures. In this manner, the silicon area may be minimized through reduction of the number of total pins and probe pads required.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: September 12, 2006
    Assignee: LSI Logic Corporation
    Inventors: Randall Bach, Jeffrey Sather
  • Patent number: 6544807
    Abstract: A process monitor includes a test circuit formed on a product die wherein the test circuit has a distribution of cell types that is substantially identical to that of the product die.
    Type: Grant
    Filed: November 3, 2000
    Date of Patent: April 8, 2003
    Assignee: LSI Logic Corporation
    Inventor: Randall Bach
  • Patent number: 6114903
    Abstract: An integrated circuit residing within a die includes at least two columns of circuits separated by a routing space. A buffer is formed within the integrated circuit for transferring signals between the integrated circuit and a location remote from the die. At least one portion of the buffer is formed as a buffer circuit column, where the buffer circuit column is aligned with a column of circuits within the integrated circuit but outside of the buffer.
    Type: Grant
    Filed: January 14, 1998
    Date of Patent: September 5, 2000
    Assignee: LSI Logic Corporation
    Inventor: Randall Bach
  • Patent number: 5751161
    Abstract: A method and circuit are disclosed for changing the output impedance of an impedance controlled buffer from an initial impedance to a final impedance, while minimizing data transmission errors. The buffer has a plurality of impedance control inputs, with each of the plurality of impedance control inputs receiving a corresponding one of a plurality of bits of a binary coded impedance control signal. The output impedance of the buffer is controlled as a function of a value of the impedance control signal. First, the value of the impedance control signal is changed from an initial value corresponding to the initial output impedance to an intermediate value corresponding to an intermediate output impedance which is less than the initial output impedance. Next, the intermediate value of the impedance control signal is changed to a final value corresponding to the final output impedance.
    Type: Grant
    Filed: April 4, 1996
    Date of Patent: May 12, 1998
    Assignee: LSI Logic Corporation
    Inventors: Shuran Wei, Randall Bach
  • Patent number: 5654895
    Abstract: A process monitor and a method of using the same to determine the relative strength of a semiconductor fabrication process are disclosed. An impedance control output from an impedance controller circuit located on a semiconductor device is retrieved. Based upon a value of the retrieved impedance control output, the relative strength of the semiconductor fabrication process used to fabricate the semiconductor device is determined.
    Type: Grant
    Filed: April 4, 1996
    Date of Patent: August 5, 1997
    Assignee: LSI Logic Corporation
    Inventors: Randall Bach, Shuran Wei
  • Patent number: 5592104
    Abstract: An output buffer having a data input terminal, a data output terminal, a predriver stage, an output stage and a resistive device. The predriver stage includes a first pull-up transistor and a first pull-down transistor which have control terminals coupled to the data input terminal and have first and second outputs, respectively. The output stage includes a second pull-up transistor and a second pull-down transistor which have control terminals coupled to the first and second outputs, respectively, and have third and fourth output terminals coupled to the data output terminal. The resistive device is coupled between the control terminals of the second pull-up and pull-down transistors.
    Type: Grant
    Filed: December 13, 1995
    Date of Patent: January 7, 1997
    Assignee: LSI Logic Corporation
    Inventor: Randall Bach