Abstract: An apparatus and method for efficient power management of multiple integrated circuits. In various implementations, a computing system includes an integrated circuit with a security processor. The security processor determines the integrated circuit transitions to an active state from a sleep state that is not intended to maintain configuration information to return to the active state without restarting an operating system. In the sleep state, multiple components of the integrated circuit have a power supply reference level turned off, which provides low power consumption for the integrated circuit. The security processor performs the bootup operation using information stored in persistent on-chip memory. By not using information stored in off-chip memory, the security processor reduces the latency of the transition.

Abstract: A computing system may implement a method for creating a first subdomain by configuring one of a first plurality of slave nodes as a first subdomain master node and configuring one or more other slave nodes of the first plurality of slave nodes as first subdomain slave nodes to the first subdomain master node.

Abstract: An apparatus and method for efficient power management of multiple integrated circuits. In various implementations, a computing system includes an integrated circuit with a security processor. The security processor determines the integrated circuit transitions to an active state from a sleep state that is not intended to maintain configuration information to return to the active state without restarting an operating system. In the sleep state, multiple components of the integrated circuit have a power supply reference level turned off, which provides low power consumption for the integrated circuit. The security processor performs the bootup operation using information stored in persistent on-chip memory. By not using information stored in off-chip memory, the security processor reduces the latency of the transition.

Abstract: A trusted processor saves and restores context and data stored at a frame buffer of a GPU concurrent with initialization of a CPU of the processing system. In response to detecting that the GPU is powering down, the trusted processor accesses the context of the GPU and data stored at a frame buffer of the GPU via a high-speed bus. The trusted processor stores the context and data at a system memory, which maintains the context and data while the GPU is powered down. In response to detecting that the GPU is powering up again, the trusted processor restores the context and data to the GPU, which can be performed concurrently with initialization of the CPU.