Abstract: A method and apparatus for improving data processing system performance having a cache. Data from one cache line is easily and quickly copied to another cache line within the cache. In the preferred embodiment, this copy cache line operation is initiated using an opcode of a central processing unit's instruction set. Thus, software running on the data processing system can invoke this cache line copy by executing this CPU instruction.Another feature is the ability to rename a cache line, again using a CPU instruction to initiate the operation. This provides a logical copy of the cache data without having to perform a physical copy.

Abstract: A controller is coupled to a plurality of registers arranged in an array having a physical configuration of N rows of registers and M columns of registers. A size register within the controller is provided for receiving a selected vector size parameter, which specifies a number of registers comprising a vector register. In response to the vector size parameter, columns in the register array are selected and concatenated to form a vector register having at least a number of registers equal to the vector size parameter. An offset parameter may be utilized to select columns that form a vector register from the M number of columns in the array. Multiple arithmetic logic units, where one arithmetic logic unit is coupled to each row of registers are utilized to perform vector operations. Any register in the array may be utilized to store a vector element or a scalar expression.

Abstract: A data processing system including a circuit for storing a plurality of instructions in a sequence together with a circuit for fetching a plurality of instructions. A circuit is provided for dispatching a plurality of the instructions to one or more processors for execution during a single computation cycle. A control circuit is connected to the dispatching circuit to delay the dispatching of an instruction. when the instruction has an execution result that is dependent upon a previous instruction execution that will set at least one bit in a condition register. The delayed instruction is delayed until that condition register has been accordingly set.

Abstract: In a data processing system configured to transfer data in words and an apparatus is provided for manipulating, in response to a single manipulation instruction, the contiguous variable length sequence of data stored in bytes including an instruction decoder for decoding a single manipulation instruction, a memory for storing data in words where each but word includes a plurality of bytes, a circuit responsive to the command signal from the instruction decoder to access a contiguous sequence of the bytes from the memory wherein the first byte of the sequence is not stored on a word boundary, and providing the byte sequence to a plurality of data processing registers wherein the first byte of the sequence is aligned with the first registered boundary. Additionally the apparatus includes the capability to provide the contiguous sequence to memory wherein the first byte of the sequence is not stored on a word boundary.

Abstract: A data processing system including a data cache with the capability to selectively zero the contents of the data cache. The invention includes a multiplexor arranged to provide a parallel data output that is greater than the parallel data input from either a central processing unit or from a memory that are each connected to access the data cache. This multiplexor is selectively controlled to provide a parallel data output of zeroes upon the decoding of a specific zeroing instruction.

Abstract: A data processing circuit that performs either a merge or Boolean logic operation on data within a single clock cycle in response to an instruction. The circuit includes a control circuit for receiving an instruction during a clock cycle and providing a plurality of control signals in response to the instruction. Data selector circuitry is included for providing a plurality of data words in response to the control signals from the control circuit. Additionally, a rotator is connected to at least one data selector for rotating at least one of the data words in response to a control signal from the control circuit. Logic circuitry is provided for logically combining bits form the rotator and the data selector circuitry in response to control signals from the control circuit for providing data output within the single clock cycle.