Abstract: A circuit verification method for a logic circuit is presented. The method includes developing a first hardware description language (HDL) code representative of the logic circuit and, for an embedded portion of the logic circuit, developing a second HDL code representative of the embedded portion. The second HDL code includes a process of forcing inputs of the embedded portion to one or more known values. The method further includes operating a processing device in conjunction with the first and second HDL codes and verifying operation of the embedded portion in response to forcing the inputs to the logic circuit.

Abstract: An integrated circuit packaging apparatus includes a first conductive layer disposed between an integrated circuit die and a conductive die paddle. Bond wires connect the first conductive layer to the lead frame package and to the integrated circuit die. A first dielectric layer is disposed between the first conductive layer and the conductive die paddle such that the first conductive layer, the first dielectric layer, and the conductive die paddle provide bypass capacitance. A method for providing bypass capacitance and power routing for an integrated circuit packaging apparatus includes; depositing a first dielectric layer on a conductive die paddle, depositing a first conductive layer on the first dielectric layer, and connecting the first conductive layer to the lead frame package and to the integrated circuit die. The first conductive layer, the first dielectric layer, and the conductive die paddle cooperate to provide bypass capacitance.

Abstract: An integrated circuit includes a first and a second die positioned on a lead frame of a package. The lead frame includes a plurality of bond fingers. The integrated circuit includes a first bond pad on the first die that is electrically interconnected to a corresponding second bond pad on the second die through first and second bond fingers of the lead frame. The package may be a QFP, DIP, PLCC, TSOP, or any other type of package including a lead frame.

Abstract: In accordance with the invention, it has been determined that the bandwidth, guaranteed periodic delivery and error correction characteristics of a USB High-Speed Interrupt OUT pipe of the USB 2.0 standard enable the Interrupt OUT pipe to be used to transfer print data from the host computer to the printer. By using the Interrupt OUT pipe for this purpose, it is no longer necessary to store an entire rasterized page in the formatter memory of the printer before commencing printing of the page. Consequently, the size of the formatter memory device can be relatively small compared to the size of the formatter memory device that is currently used to store an entire rasterized page. Alternatively, the same size memory device as that currently used to store an entire rasterized page may be used to enable higher resolution pages to be printed.

Abstract: A Quad Flat Pack (QFP) package which includes first and second dies arranged in a side-by-side orientation, and a power supply bus which protrudes between adjacent sides of the first and second dies and which supplies power to the adjacent sides via connections to the adjacent sides.

Abstract: A host-based color printing system having a color printing accelerator module that assists the host processor in order to speed up the rate at which color formatting tasks are performed by the host. The color printing accelerator module has an I/O interface that connects to a first I/O port of the host computer of the host-based color printing system. A second I/O port of the host computer connects to an I/O interface of the printer. After the color formatting tasks have been performed by the host computer and the color printing accelerator module, the processed data is sent from the host computer to the printer for printing.

Abstract: An integrated circuit includes a first die and a second die positioned in a package. The first die has a redistribution layer formed on the die and including a plurality of relocated bond pads. The relocated bond pads are positioned near an inner edge of the first die that is adjacent to an inner edge of the second die. Each relocated bond pad is coupled to a corresponding bond pad on the second die through a respective bonding wire. The first die further includes a plurality of original bond pads. The redistribution layer further includes at least one intermediate bond pad electrically interconnected through a respective conductive trace to a corresponding original bond pad. Each intermediate bond pad is electrically connected to a corresponding relocated bond pad through a respective bond wire.

Abstract: An integrated circuit includes a first and a second die positioned on a lead frame of a package. The lead frame includes a plurality of bond fingers. The integrated circuit includes a first bond pad on the first die that is electrically interconnected to a corresponding second bond pad on the second die through first and second bond fingers of the lead frame. The package may be a QFP, DIP, PLCC, TSOP, or any other type of package including a lead frame.

Abstract: An integrated circuit or chip includes a first die and a second die positioned on a lead frame of a package including a lead frame, such as a QFP, DIP, PLCC, TSOP, or any other type of package including a lead frame. The integrated circuit further includes a redistribution layer formed on the first die to couple selected bond fingers of the lead frame to selected bonding pads of the first and second die. The selected bond fingers may correspond to bond fingers that receive a first supply voltage or the first supply voltage and a second supply voltage.

Abstract: An integrated circuit or chip includes a first die and a second die positioned on a lead frame of a package including a lead frame, such as a QFP, DIP, PLCC, TSOP, or any other type of package including a lead frame. The integrated circuit further includes a redistribution layer formed on the first die to couple selected bond fingers of the lead frame to selected bonding pads of the first and second die. The selected bond fingers may correspond to bond fingers that receive a first supply voltage or the first supply voltage and a second supply voltage.

Abstract: An image enhancement component of an image processing pipeline preferably uses a single lookup table (LUT) to convert M-bit Red (R), Green (G) and Blue (B) values into respective N-bit R, G and B values, where N is greater than M. Preferably, the N-bit values are determined based on the inverse of an algorithm performed upstream of the image enhancement component by an image correction component. The N-bit R, G and B values provide the image with an improved signal-to-noise ratio (SNR).

Abstract: A printer includes a print engine and a monochrome formatter connected to the print engine and being operatively connectable to a color chip. A monochrome print engine and a monochrome formatter provide a monochrome printer. A color print engine and a monochrome formatter operatively connected to a color chip provide a color printer.

Abstract: An integrated circuit packaging apparatus includes a first conductive layer disposed between an integrated circuit die and a conductive die paddle. Bond wires connect the first conductive layer to the lead frame package and to the integrated circuit die. A first dielectric layer is disposed between the first conductive layer and the conductive die paddle such that the first conductive layer, the first dielectric layer, and the conductive die paddle provide bypass capacitance. A method for providing bypass capacitance and power routing for an integrated circuit packaging apparatus includes; depositing a first dielectric layer on a conductive die paddle, depositing a first conductive layer on the first dielectric layer, and connecting the first conductive layer to the lead frame package and to the integrated circuit die. The first conductive layer, the first dielectric layer, and the conductive die paddle cooperate to provide bypass capacitance.

Abstract: A USB to PCI bridge preferably includes a USB interface, a PCI interface, and an on-board processor configured to manage data flow between the interfaces. Firmware is preferably provided and configured to translate signals between the USB and PCI interfaces. The bridge can also include an internal memory configured to store instructions and data. A PCI central resource can be provided to enable hosting of a PCI subsystem. In a preferred embodiment, a plurality of PCI targets can be connected to a USB port through the bridge.

Abstract: An ATA device access system preferably includes surrogate registers that correspond to ATA registers. A command register can be configured to control data transfer between the ATA and surrogate registers. A status register can be configured to signal completion of data transfer to or from the surrogate registers. Using the ATA device access system, data can be written to the surrogate registers during a write operation with little or no wait and then transferred to the ATA registers without tying up a bus or a processor. Similarly, data can be loaded into the surrogate registers from the ATA registers during a read operation with little or no wait, before being read from the surrogate registers by a processor.

Abstract: Reset circuitry for an integrated circuit is presented. An internal oscillator produces an oscillating signal upon power-up of the integrated circuit. The internal oscillator is not dependent on signals generated outside the integrated circuit. An electro-static discharge blocker circuit receives an external reset signal generated outside the integrated circuit. The electrostatic discharge blocker circuit utilizes the oscillating signal to perform electro-static discharge blocking for the external reset signal to produce an internal reset signal.

Abstract: A printer includes a print engine and a monochrome formatter connected to the print engine and being operatively connectable to a color chip. A monochrome print engine and a monochrome formatter provide a monochrome printer. A color print engine and a monochrome formatter operatively connected to a color chip provide a color printer.

Abstract: A method of enumerating a peripheral device preferably includes initiating operation of the device in a low-power mode. Power can be conserved, for instance, by slowing processor speed or by shutting off clocks to one or more unneeded blocks of the peripheral device during enumeration. During enumeration, a host computer preferably obtains enumeration information from the peripheral device and then uses that information to select a configuration state for operating the device following enumeration.

Abstract: Apparatus for writing compressed data to a storage device having multiple storage areas. The apparatus identifies one or more storage areas to receive the compressed data based upon the compression ratio of the compressed data and the characteristic transfer rates of the storage areas. The apparatus then writes the compressed data to the Identified storage areas. This is accomplished so that when the compressed data is later read, the storage device has at least a minimum output rate. The storage device may, for example, be a disk storage unit for a laser printer. The compressed data may be compressed video data describing a document to be printed.

Abstract: A data processing system includes a first bus which couples a processor and other components and is configured to operate in accord with a standard protocol. Plural functional modules, each performing a function required by the data processing system are coupled to a second bus. The second bus includes dedicated read/write enable lines for each functional module and plural data lines coupled in common to all functional modules. A bridge module includes a controller which is coupled between the first and second busses. The controller is responsive to a read or write command received from the processor, to apply a logic signal to the read/write enable circuits coupled to a functional module designated by the received command. The functional module responds by either providing the requested data onto the data lines of the second bus or receiving data from the second bus into the functional module, as the case may be.